Conferences in DBLP
T. Sato , M. Nakajima , T. Sukemura , G. Goto A Regularly Structured 54-bit Modified-Wallace-Tree Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Guyot , Y. Kusumaputri OCAPI: A Prototype for High Precision Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] O. C. McNally , John V. McCanny , Roger F. Woods Design of a Highly Pipelined 2nd Order IIR Filter Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Sparsø , Steen Pedersen , Erik Paaske Design of a Fully Parallel Viterbi Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] R. Nagalla , Laurence E. Turner Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry R. Burch , Edmund M. Clarke , David E. Long Symbolic Model Checking with Partitioned Transistion Relations. [Citation Graph (0, 0)][DBLP ] Conf ] Eleanor M. Mayger , Michael P. Fourman Integration of Formal Methods with System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Geraint Jones , Mary Sheeran Deriving Bit-Serial Circuits in Ruby. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Schneider , Ramayya Kumar , Thomas Kropf Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Konrad Doll , Frank M. Johannes , Georg Sigl DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Mayrhofer , Massoud Pedram , Ulrich Lauther A Flow-Oriented Approach to the Placement of Boolean Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Habib Youssef , Rung-Bin Lin , Eugene Shragowitz Bounds on Net Delays for Physical Design of Fast Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Karl-Heinz Erhard , Frank M. Johannes Area Minimisation of IC Power/Ground Nets by Topology Optimisation. [Citation Graph (0, 0)][DBLP ] Conf ] Herbert Bauer , Christian Sporrer , Thomas H. Krodel On Distributed Logic Simulation Using Time Warp. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Brunvand , M. Starkey An Integrated Environment for the Design and Simulation of Self-Timed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tom J. Kazmierski , Andrew D. Brown , Ken G. Nichols , Mark Zwolinski A General Purpose Network Solving System. [Citation Graph (0, 0)][DBLP ] Conf ] Peter B. Denyer , David S. Renshaw , Gouyu Wang , Ming Ying Lu , Stuart Anderson On-Chip CMOS Sensors for VLSI Imaging Systems. [Citation Graph (0, 0)][DBLP ] Conf ] J. Quali , Gabriele Saucier , P. Y. Alla , Jacques Trilhe , L. Masse-Navette A Customizable Neural Processor for Distributed Neural Network. [Citation Graph (0, 0)][DBLP ] Conf ] Daniele D. Caviglia , Maurizio Valle , Giacomo M. Bisio A VLSI Module for Analog Adaptive Neural Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] A. Richard Newton Has CAD for VLSI Reached a Dead End? [Citation Graph (0, 0)][DBLP ] Conf ] Werner Geurts , Stefaan Note , Francky Catthoor , Hugo De Man Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Norbert Wehn , J. Biesenack , Michael Pilsl A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Amine Jerraya , Pierre G. Paulin , Simon Curry Meta VHDL for Higher Level Controller Modeling and Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Philip A. Wilsey , Timothy J. McBrayer , David Sims Towards a Formal Model of VLSI Systems Compativle with VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Glunz , Gerd Venzl Hardware Design Using CASE Tools. [Citation Graph (0, 0)][DBLP ] Conf ] A. Laudenbach , Manfred Glesner , Norbert Wehn A VLSI System Design for the Control of High Performance Combustion Engines. [Citation Graph (0, 0)][DBLP ] Conf ] Patrice Frison , Dominique Lavenier A Fully Integrated Systolic Spelling Co-Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfram Liebsch , K. Boettcher Parallel Architecture and VLSI Implementation of a 80MHz 2D-DCT 80 MHz 2D-DCT/ICDT Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , A. Richard Newton Exact Redundant State Registers Removal Based on Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] P. F. Yeung , D. J. Rees Resources Restricted Global Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] M. Schönfeld , M. Schwiegershausen , Peter Pirsch Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Marina Zanella , Paolo Gubian Workspace and Methodology Management in the Octtools Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Madsen Single-Level Wiring for CMOS Functional Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi R. Pai , S. S. S. P. Rao An Over-the-Cell Channel Router. [Citation Graph (0, 0)][DBLP ] Conf ] M. Starkey , Tony M. Carter Switchbox Routing by Pattern Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Donald F. Beal , Costas Lambrinoudakis GPFP: A SIMD PE for Higher VLSI Densities. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne P. Buleson , Louis L. Scharf Input/Output Design for VLSI Array Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Faergemand Nielsen , Poul Martin Rands Jensen , Kallol Kumar Bagchi , Ole Olsen Comparing Transformation Schemes for VLSI Array Processor Design - A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsumasa Koyanagi A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Farhad Aghdasi Pass-Transistor Self-Clocked Asynchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] C. Thomas Gray , Thomas A. Hughes , Sanjay Arora , Wentai Liu , Ralph K. Cavin III Theoretical and Practical Issues in CMOS Wave Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Naser Awad , David R. Smith Automatic Interfacing of Synchronous Modules to an Asynchronous Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Klaassen How to Compare Analog Results. [Citation Graph (0, 0)][DBLP ] Conf ] Bulent I. Dervisoglu , Gayvin E. Stong Application of Scan-Based DFT Methodology for Detecting Static and Timing Failures in VLSI Components. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Franc Brglez , Gershon Kedem Identification and Resynthesis of Pipelines in Sequential Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Albert van der Werf , B. T. McSweeney , Jef L. van Meerbergen , Paul E. R. Lippens , W. F. J. Verhaeg Hierarchical Retiming Including Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Ellen Sentovich , Robert K. Brayton Preserving Don't Care Conditions During Retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Schimmler , Hartmut Schmeck A Fault Tolerant and High Speed Instruction Systolic Array. [Citation Graph (0, 0)][DBLP ] Conf ] Guoning Liao A Reconfigurable Fault Tolerant Module Approach to the Reliability Enhancement for Mesh Connected Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Ian P. Jalowiecki , Stephen J. Hedge The WASP 2 Wafer Scale Integration Demonstrator. [Citation Graph (0, 0)][DBLP ] Conf ] 