Conferences in DBLP
Werner Weber Ambient Intelligence - Key Technologies in the Communication Age. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:1- [Conf ] Shekhar Borkar Exponential Challenges, Exponential Rewards - The future of Moore's Law. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:2- [Conf ] Andreas Kirschbaum Towards safer cars - Microeletronics in Automotive. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:3- [Conf ] Radu Marculescu Designing Application Specific Networks-On-Chip: Five easy pieces. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:5- [Conf ] Narayanan Vijaykrishnan Energy Efficient and Reliable System Design. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:6-9 [Conf ] Klaus Winkelmann Formal Verification. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:10-0 [Conf ] Andreas Hermann , Markus Olbrich , Erich Barke Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:13-18 [Conf ] Johanna Tuominen , Pasi Liljeberg , Jouni Isoaho Self-Timed Approach for Reducing On-Chip Switching Noise. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:19-24 [Conf ] João M. S. Silva , Luis Miguel Silveira Dynamic Models for Substrate Coupling in Mixed-Mode Systems. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:25-30 [Conf ] Timm Ostermann , Wolfgang Gut , Christian Bacher , Bernd Deutschmann Measures to Reduce the Electromagnetic Emission of a SoC. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:31-0 [Conf ] Philippe Coussy , Adel Baganne , Eric Martin Communication and Timing Constraints Analysis for IP Design and Integration. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:38-43 [Conf ] Thomas Hollstein , Ralf Ludewig , Christoph Mager , Peter Zipf , Manfred Glesner A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:44-49 [Conf ] Maciej Borkowski , Juha Häkkinen , Juha Kostamovaara A Sigma-Delta Modulator Development Environment for Fractional-N Frequency Synthesis. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:50-54 [Conf ] Axel G. Braun , Jan B. Freuer , Joachim Gerlach , Wolfgang Rosenstiel Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:55-0 [Conf ] Cristian Chitu , Manfred Glesner High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of Operation. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:62-67 [Conf ] Nicolas Sklavos , Odysseas G. Koufopavlou Architectures and FPGA Implementations of the SCO(-1, -2, -3) Ciphers Family. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:68-73 [Conf ] Christophe Layer High Performance System Architecture of an Associative Computing Engine Optimised for Search Algorithms. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:74-0 [Conf ] Nicole Drechsler , Rolf Drechsler Exploration of Sequential Depth by Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:81-85 [Conf ] Dominique Borrione , Menouer Boubekeur , Laurent Mounier , Marc Renaudin , Antoine Sirianni Validation of asynchronous circuit specifications using IF/CADP. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:86-91 [Conf ] Anneliese Amschler Andrews , Andrew O'Fallon , Tom Chen A Rule-Based Software Testing Method for VHDL Models. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:92-0 [Conf ] Arkadiy Morgenshtein , Michael Moreinis , Israel A. Wagner , Avinoam Kolodny Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:99-104 [Conf ] Marios Kesoulis , Dimitrios Soudris , C. Koukourlis , Adonios Thanailakis Designing Low Power Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:105-110 [Conf ] José Augusto Miranda Nacif , Flávio Miana de Paula , Harry Foster , Claudionor José Nunes Coelho Jr. , Antônio Otávio Fernandes The Chip is Ready. Am I done? On-chip Verification using Assertion Processors. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:111-0 [Conf ] Ali Ahmadinia , Jürgen Teich Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:118-122 [Conf ] Young-Su Kwon , Woo-Seung Yang , Chong-Min Kyung Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:123-128 [Conf ] Jürgen Becker , Michael Hübner , Michael Ullmann Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:129-0 [Conf ] G. Bonfini , C. Garbossa , Roberto Saletti A Switched Opamp-based 10-b Integrated ADC for Ultra Low-power Applications. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:136-141 [Conf ] Glenn Wolfe , Mengmeng Ding , Ranga Vemuri Adaptive Sampling and Modeling of Analog Circuit Performance Parameters. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:142-0 [Conf ] Péter Szántó , Béla Fehér 3D rendering using FPGAs. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:149-154 [Conf ] Hans-Joachim Stolberg , Mladen Berekovic , Lars Friebe , Sören Moch , Mark Bernd Kulaczewski , Peter Pirsch HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:155-160 [Conf ] Thilo Pionteck , Lukusa D. Kabulepa , Manfred Glesner Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:161-166 [Conf ] Mihail Petrov , Abdulfattah Mohammad Obeid , Tudor Murgan , Peter Zipf , Jörg Brakensiek , Bernard Ölkrug , Manfred Glesner An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:167-0 [Conf ] Alexandre M. Amory , Leandro A. Oliveira , Fernando Gehm Moraes Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:174-179 [Conf ] Wei Zou , C. N. Chu , Sudhakar M. Reddy , Irith Pomeranz Optimizing SOC Test Resources using Dual Sequences. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:180-185 [Conf ] Elham Safi , Reihaneh Saberi , Zohreh Karimi , Zainalabedin Navabi Processor Testing Using an ADL Description and Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:186-0 [Conf ] Cristiano Lazzari , Cristiano Viana Domingues , José Luís Almada Güntzel , Ricardo Augusto da Luz Reis A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:193-197 [Conf ] Pavel V. Nikitin , Winnie Yam , C.-J. Richard Shi Parametric Equivalent Circuit Extraction for VLSI Structures. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:198-203 [Conf ] Renato Fernandes Hentschke , Marcelo de Oliveira Johann , Ricardo Augusto da Luz Reis A study on the performance of fast initial placement algorithms. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:204-0 [Conf ] Juha Häkkinen , Maciej Borkowski , Juha Kostamovaara A PLL-Based RF Synthesizer Test System. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:211-214 [Conf ] Shervin Sharifi , Mohammad Hosseinabady , Zainalabedin Navabi Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:215-220 [Conf ] Andrea S. Brogna , Franco Bigongiari , Silvia Chiusano , Paolo Prinetto , Roberto Saletti Designing and Testing High Dependable Memories for Aerospace Applications. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:221-0 [Conf ] Tapio Ristimäki , Jari Nurmi Reprogrammable Algorithm Accelerator IP Block. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:228-232 [Conf ] Nikolaos Kavvadias , Spiridon Nikolaidis Tradeoffs in the Design Space Exploration of Application-Specific Processors. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:233-238 [Conf ] Antonio Carlos Schneider Beck , Luigi Carro Low Power Java Processor for Embedded Applications. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:239-0 [Conf ] Stephan Henzler , Markus Koban , Doris Schmitt-Landsiedel , Jörg Berthold , Georg Georgakos Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:246-251 [Conf ] Adam Golda , Andrzej Kos Static Versus Dynamic Power Losses in CMOS VLSI Systems Considering Temperature. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:252-257 [Conf ] Casper Lageweg , Sorin Cotofana , Stamatis Vassiliadis Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:258-262 [Conf ] Alan J. Drake , Kevin J. Nowka , Richard B. Brown Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:263-0 [Conf ] Chia-Ming Hsu , Tien-Fu Chen Flexible Heterogeneous Multicore Architectures for Media Processing via Customized Long Instruction Words. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:270-275 [Conf ] Daniel Mesquita , Lionel Torres , Fernando Gehm Moraes , Gilles Sassatelli , Michel Robert Are coarse grain reconfigurable architectures suitable for cryptography? [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:276-281 [Conf ] Karim Ben Chehida , Michel Auguin Partitioning Reactive Data Flow Applications On Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:282-287 [Conf ] Jürgen Becker , Alexander Thomas , Maik Scheer Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:288-0 [Conf ] Tuomas Järvinen , Perttu Salmela , Teemu Sipilä , Jarmo Takala In-Place Storage of Path Metrics in Viterbi Decoders. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:295-300 [Conf ] Juan Manuel García Chamizo , Maria Teresa Signes Pont , Higinio Mora Mora , Gregorio de Miguel Casado Hough Transform recursive evaluation using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:301-306 [Conf ] Eduardo A. C. da Costa , José Monteiro , Sergio Bampi Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:307-0 [Conf ] Zahid Khan , Tughrul Arslan , Ahmet T. Erdogan Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:314-317 [Conf ] Fernando Gehm Moraes , Aline Mello , Leandro Möller , Luciano Ost , Ney Laert Vilar Calazans A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:318-323 [Conf ] Michael S. McCorquodale , Eric D. Marsman , Robert M. Senger , Fadi H. Gebara , Richard B. Brown Microsystem and SoC Design with UMIPS. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:324-0 [Conf ] Valentina Ciriani , Anna Bernasconi , Rolf Drechsler Testability of SPP Three-Level Logic Networks. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:331-336 [Conf ] Ilia Polian , Bernd Becker Reducing ATE Cost in System-on-Chip Test. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:337-342 [Conf ] Maciej Bellos , Xrysovalantis Kavousianos , Dimitris Nikolos , Dimitri Kagaris DV-TSE: Difference Vector Based Test Set Embedding. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:343-0 [Conf ] Juan Manuel García Chamizo , Jerónimo Mora Pascual , Higinio Mora Mora , Maria Teresa Signes Pont Calculation Methodology for Flexible Arithmetic Processing. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:350-355 [Conf ] Radu Dogaru , Cristian Chitu , Manfred Glesner A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and Applications. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:356-361 [Conf ] Dinesh Pamunuwa , Johnny Öberg , Li-Rong Zheng , Mikael Millberg , Axel Jantsch Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:362-0 [Conf ] Shrutin Ulman Delay and Short Circuit Power Estimation for a Submicron CMOS Inverter driving a CRC-PI Interconnect Load. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:369-374 [Conf ] Martin Margala , Quentin Diduck , Eric Moule 1.8V 0.18µm CMOS Novel Successive Approximation ADC. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:375-379 [Conf ] Martin Margala , John Liobe , Quentin Diduck Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:380-385 [Conf ] Martin Margala , Magdy A. El-Moursy , Ali El-Moursy , Junmou Zhang , Wendi Beth Heinzelman 1-V ADPCM Processor for Low-Power Wireless Applications. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:386-393 [Conf ] Ehsan Atoofian , Zainalabedin Navabi A Low Power BIST Architecture for FPGA Look-Up Table Testing. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:394-397 [Conf ] Adão Antônio de Souza Jr. , Luigi Carro An All-Digital ADC for Instrumentation within SOCs. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:398-403 [Conf ] Diego Caldas Salengue , João Baptista Martins , Cesar Ramos Rodrigues , André Luiz Aita FPGA Implementation of a VVI Temporary Pacemaker Digital Control. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:404-409 [Conf ] Fernando da Rocha Paixão Cortes , Eric E. Fabris , Sergio Bampi Applying the GM/ID method in the analysis and design of Miller Amplifier, Comparator and GM-C PASS-B. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:410-415 [Conf ] Hemanth Sampath , Ranga Vemuri MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:416-421 [Conf ] André Luiz Aita , João Baptista Martins , César A. Prior , Cesar Ramos Rodrigues Low-Power High-CMRR CMOS Instrumentation Amplifier for Biomedical Applications. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:422-425 [Conf ] Giuseppe Ascia , Vincenzo Catania , Maurizio Palesi A Genetic Approach To Bus Encoding. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:426-431 [Conf ] Arturo Méndez Patiño , Marcos Martínez Peiró 2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:432-438 [Conf ] Jari Nikara , Stamatis Vassiliadis , Jarmo Takala , Petri Liuha FPGA-Based Variable Length Decoders. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:437-441 [Conf ] Stephan Bingemer , Peter Zipf , Manfred Glesner An Integrated Model Bridging the Gap between Technology and Economy. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:442-0 [Conf ]