Conferences in DBLP
Joseph Borel , J. Monnier , G. Matheron The single chip system era. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel R. Brasen , Arnold Ginetti Post-placement technology mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Shigehiro , Takashi Nagata , Isao Shirakawa , Takashi Kambe Optimal layout recycling based on graph theoretic linear programming approach. [Citation Graph (0, 0)][DBLP ] Conf ] Kim-Minh Nguyen , Martin C. Lefebvre A family of module generators for the layout synthesis of I/O buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Lorenz Ladage , Georg Lodde A 45° compaction algorithm handling overconstraints. [Citation Graph (0, 0)][DBLP ] Conf ] Hermann Hauser Personal Communicators: A better way to stay in touch. [Citation Graph (0, 0)][DBLP ] Conf ] Imed Moussa , Ali Skaf , Alain Guyot Design of a GaAs redundant divider. [Citation Graph (0, 0)][DBLP ] Conf ] Poul Martin Rands Jensen An ASIC array architecture for the DITPOS algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] J. Morris Chang , Edward F. Gehringer Performance of object caching for object-oriented systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Skaf , Jean-Claude Bajard , Alain Guyot , Jean-Michel Muller A VLSI circuit for on-line polynominal computing: Application to exponential, trigonometric and hyperbolic functions. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gössel , Egor S. Sogomonyan Self-parity cominational circuits for self-testing, concurrent fault detection and parity scan design. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele Partitioning and hierarchical description of self-testable designs. [Citation Graph (0, 0)][DBLP ] Conf ] Régis Leveugle Test of single fault tolerant controllers in VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] W. A. J. Waller , S. M. Aziz A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic. [Citation Graph (0, 0)][DBLP ] Conf ] D. Poussart Opportunities for integrating early-vision computation algorithms and VLSI technology to the development of smart sensors. [Citation Graph (0, 0)][DBLP ] Conf ] J. Schönfeld , Peter Pirsch Single board image processing unit for vehicle guidance. [Citation Graph (0, 0)][DBLP ] Conf ] Jaap Smit , Mark J. Bentum , M. M. Samsom Implementation of the volume rendering algorithm using a low-power design-style. [Citation Graph (0, 0)][DBLP ] Conf ] D. Jacquet , Gabriele Saucier Design of a dedicated neural network on silicon: application to optical character recognition. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Muller ARM6: Processor design for high performance at low power. [Citation Graph (0, 0)][DBLP ] Conf ] Albert van der Werf , Emile H. L. Aarts , E. W. Heijnen , Jef L. van Meerbergen , Wim F. J. Verhaegh , Paul E. R. Lippens A new method for retiming multi-functional processing units. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Gopalakrishnan , Venkatesh Akella A transformational approach to asynchronous high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen B. Furber , P. Day , Jim D. Garside , N. C. Paver , J. V. Woods A micropipelined ARM. [Citation Graph (0, 0)][DBLP ] Conf ] F. Poirier , Jean-Claude Heudin , M. Belleville , C. Jaffard A high performance RISC microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Röthig , Elmar U. K. Melcher , Michel Dana Probabilistic power consumption estimation in digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Maximilian Erbar , Ingo Könenkamp , Ernst-Helmut Horneber Solving the partial differential equations of transmission lines with wave digital filters. [Citation Graph (0, 0)][DBLP ] Conf ] M. Schneider , Utz Wever , Qinghua Zheng Parallel harmonic balance. [Citation Graph (0, 0)][DBLP ] Conf ] Norbert Wehn , Manfred Glesner , C. Vielhauer Estimating lower hardware bounds in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Christer Svensson , Jiren Yuan Ultra high speed CMOS design. [Citation Graph (0, 0)][DBLP ] Conf ] Claus M. Habiger , Ian P. Jalowiecki The implementation of a MCM associative string processor. [Citation Graph (0, 0)][DBLP ] Conf ] Bertrand Cabon , T. V. Dinh , J. Chilo Superconductive interconnections in multi-chip modules. [Citation Graph (0, 0)][DBLP ] Conf ] Mikiko Sode Tanaka , Masaki Ishikawa A multilayer channel router based on optimal multilayer net assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin Bolding , Sen-Ching Cheung , Sung-Eun Choi , Carl Ebeling , Soha Hassoun , Ton Anh Ngo , Robert Wille The chaos router chip: design and implementation of an adaptive router. [Citation Graph (0, 0)][DBLP ] Conf ] Tianxiong Xue , Takashi Fujii , Ernest S. Kuh A new performance-driven global routing algorithm for gate array. [Citation Graph (0, 0)][DBLP ] Conf ] Shen Lin , Ernest S. Kuh Circuit simulation for large interconnected IC networks. [Citation Graph (0, 0)][DBLP ] Conf ] M. Müller Bondgraph execution as a new algorithm for circuit simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Avinash C. Palaniswamy , Philip A. Wilsey Adaptive checkpoint intervals in an optimistically synchronised parallel digital system simulator. [Citation Graph (0, 0)][DBLP ] Conf ] 