Conferences in DBLP
Fred L. Anderson IV , José G. Delgado-Frias A Reconfigurable Switch for a DSP Array. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:3-6 [Conf ] Christian Panis , Gunther Laure , Wolfgang Lazian , Herbert Grünbacher , Jari Nurmi A Branch File for a Configurable DSP Core. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:7-12 [Conf ] Hoon Na , Dae-Gwon Jeong MPEG-4 HVXC Real-Time Implementation on Floating Point DSP. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:13-20 [Conf ] Mitchell J. Myjak , José G. Delgado-Frias A Two-Level Reconfigurable Architecture for Digital Signal Processing. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:21-27 [Conf ] Deshanand P. Singh , Terry P. Borer , Stephen Dean Brown Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:28-33 [Conf ] X. Zhang , Gabriel Dragffy , Anthony G. Pipe Bio-Inspired Reconfigurable Architecture for Reliable Systems. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:34-40 [Conf ] Deshanand P. Singh , Stephen Dean Brown An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:41-50 [Conf ] Hussain Al-Asaad , Alireza Sarvi Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:51-57 [Conf ] Daniel R. Blum , José G. Delgado-Frias A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:58-64 [Conf ] Jie Han , Pieter Jonker A Study on Fault-Tolerant Circuits Using Redundancy. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:65-69 [Conf ] Robert Chun , Linda Yang Reuse of Firmware Tests in System-On-Chip Design Verification. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:70-78 [Conf ] Jiyi Gu , Majid Ahmadi , William C. Miller A Low-Voltage Low-Power Digital-Audio Sigma-Delta Modulator in 0.18-µm CMOS. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:79-82 [Conf ] Anilkumar Patro , Ashish Mishra Lower Power Processor Design Issues. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:83-86 [Conf ] Jaime Ramírez-Angulo , Shanta Thoutam , Gladys Omayra Ducoudray , Ramón González Carvajal A New Power Efficient Fully Differential Low-Voltage Two Stage OP-AMP Architecture. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:87-91 [Conf ] Naresh Sarwabhotla , Arthi Kothandaraman A Power-Efficient Level Converter Design For Multi-Supply Voltage CMOS Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:92-96 [Conf ] Arifur Rahman Models for Full-Chip Power Dissipation in Field Programmable Gate Arrays and the Impact of Subthreshold Leakage Current. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:97-106 [Conf ] Thomas Eschbach , Wolfgang Günther , Bernd Becker Cross Reduction for Orthogonal Circuit Visualization. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:107-113 [Conf ] Janet Meiling Wang , Pinhong Chen , Omar Hafiz Switching Windows Computation in Presence of Crosstalk Noise. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:114-118 [Conf ] Nathaniel Bird , Ethan S. Miller , Paul J. Pfeiffer , Srinivasa Vemuru Channel Routing with Crosstalk Consideration. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:119-124 [Conf ] Sumeer Goel , Mohamed A. Elgamel , Magdy A. Bayoumi Energy Efficient and Noise-Tolerant XOR-XNOR Circuit Design. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:125-130 [Conf ] Manfred Schimmler , Bertil Schmidt , Hans-Werner Lang , Sven Heithecker An Area-Efficient Bit-Serial Integer Multiplier. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:131-137 [Conf ] Ali Telli , Simsek Demir , Murat Askar Planar Spiral Inductor Modeling for RFIC Design. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:138-142 [Conf ] Scott C. Smith Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:143-149 [Conf ] Volnei A. Pedroni High-Resolution WTA-MAX Circuit for Large Networks. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:150-154 [Conf ] Adnan M. Lokhandwala , Sudip K. Mazumder A Novel Smart Power ASIC (SPIC) for Integrated Control of Cascaded Power Converters. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:155-161 [Conf ] Youngsoo Kim , Janghong Yoon , Sungok Kim An Improved Circuit Design for Parallel Sequence Generation. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:162-165 [Conf ] Khia-Ho Chang , Bah-Hwee Gwee , Joseph Sylvester Chang A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:166-172 [Conf ] Yil Suk Yang , Jongdae Kim , Tae Moon Roh , Dae Wood Lee , Sung-Ku Kwon , Il Yong Park , Byoung Gon Yu Level Shifter Circuit Having Dual Outputs for FPD Gate Driver. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:173-177 [Conf ] Satish K. Bandapati , Scott C. Smith Design and Characterization of NULL Convention Arithmetic Logic Units. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:178-184 [Conf ] Kang Hyeon Rhee A Study on the 8bit Pipeline RISC Processor. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:185-189 [Conf ] Evandro de Araújo Jardini , Dilvan de Abreu Moreira Multithreaded parallel VLSI Leaf Cell Generator Using Agents 2. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:190-196 [Conf ] Noboru Watanabe Foundation of Quantum Capacity. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:197-202 [Conf ] Satoshi Ikeda , Izumi Kubo , Masafumi Yamashita Reducing the Hitting and the Cover Times of Random Walks on Finite Graphs by Local Topological Information. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:203-207 [Conf ] Luigi Accardi , Masanori Ohya A Stochastic Limit Approach to the SAT Problem. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:208-216 [Conf ] Amardeep Singh Quantum Search Algorithm for Automated Test Pattern Generation in VLSI Testing. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:217-223 [Conf ] L. Kalyan Kumar , Aditya S. Ramani , Amol J. Mupid , V. Kamakoti , Sivaprakasam Suresh On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:224-232 [Conf ] Yiming Li , Shao-Ming Yu , Hsiao-Mei Lu Intelligent Device Parameter Extraction for Nanoscale MOSFETs Era. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:233-239 [Conf ] J. K. Kim , S. H. Won , Ki-Seok Chung , H. D. Cho , T. W. Kang , T. S. Nam , C. S. Kang , C. H. Yi , D. S. Kim Properties of A1/BaTa2O6/GaN MIS Structure. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:240-243 [Conf ] Shih-Ching Lo , Jyun-Hwei Tsai , Jer-Ming Hsu , Yiming Li Quantum Mechanical Gate Current Simulation in MOSFETs with Ultrathin Oxides. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:244-250 [Conf ] Jam Wem Lee , Yiming Li , Howard Tang Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit Design. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:251-260 [Conf ] Sankalp Kallakuri , Alex Doboli , Simona Doboli Applying Stochastic Modeling to Bus Arbitration for Network-On-Chip Systems. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:261-265 [Conf ] Keun Soo Yim , Kern Koh , Hyokyung Bahn A Compressed Page Management Scheme for NAND-Type Flash Memory. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:266-271 [Conf ] Ling Wang , Yingtao Jiang , Henry Selvaraj Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:272-278 [Conf ] Seung Wook Lee , Jong Tae Kim Universal Reed-Solomon Decoder Using Hardware/Software Co-Design Method. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:279-284 [Conf ] Manfred Schimmler , Viktor Bunimov A Simple Circuit to Reduce the Search Range for Large Prime Numbers. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:285-291 [Conf ] Rita M. Hare , Bryant A. Julstrom A Genetic Algorithm for Restricted Cases of the Rectilinear Steiner Problem with Obstacles. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:292-297 [Conf ] Todd W. Neller , David C. Hettlinger Learning Annealing Schedules for Channel Routing. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:298-302 [Conf ] Andris Ambainis , Uldis Barbans , Agnese Belousova , Aleksandrs Belovs , Ilze Dzelme , Girts Folkmanis , Rusins Freivalds , Peteris Ledins , Rihards Opmanis , Agnis Skuskovniks Size of Quantum Versus Deterministic Finite Automata. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:303-308 [Conf ] Lelde Lace , Rusins Freivalds Lower Bounds for Query Complexity of Some Graph Problems. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:309-316 [Conf ] Hirotsuga Kajisaki , Takakazu Kurokawa SEBSW-2: SEcret-Key Block Cipher SWitcher. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:317-323 [Conf ] Gene Eu Jan , Chiou-Min Shen , Shao-Wei Leu , Cheng-Hung Li The Design and Analysis of an Elliptic Curve Cryptosystem. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:324-328 [Conf ] Gene Eu Jan , Lokar J. Y. Lin , W. R. Liou , Y. Y. Chen The Design and Implementation of a 2048-Bit RSA Encryption/Decryption Chip. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:329-338 [Conf ] Mitra Mirhassani , Majid Ahmadi , William C. Miller A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:339-344 [Conf ] Jaime Ramírez-Angulo , Chandrika Durbha , Gladys Omayra Ducoudray , Ramón González Carvajal Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:345-350 [Conf ] Bhupen P. Zaveri Phase Coincidence Technique for Frequency Difference Measurement. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:351-355 [Conf ] Jae-Young Yi , Yong-Hui Lee , Cheon-Hee Yi PEDE (Plasma Edge Damage Effect) Curing by Various Heat Treatment. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:356-360 [Conf ] Vishal Verma , Himanshu Thapliyal A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:361-365 [Conf ] YunKyung Lee , Youngsu Park High Speed, Small Area AES Block Cipher Coprocessor Design for USIM Card. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:366-372 [Conf ] Srinivasa Vemuru Simultaneous Switching Noise Estimation Including the Effects of the Driving Transistor Gate-Source Capacitance. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:373-378 [Conf ] Scott F. Smith The Advanced Encryption Standard on an Asynchronous Shared-Memory Multiprocessor. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:379-381 [Conf ] Suleyman Tosun , Hakduran Koc , Nazanin Mansouri Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs. [Citation Graph (0, 0)][DBLP ] VLSI, 2003, pp:382-0 [Conf ]