Conferences in DBLP
Pradip Bose Power-Aware, Reliable Microprocessor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sachin S. Sapatnekar , Jaijeet S. Roychowdhury , Ramesh Harjani High-Speed Interconnect Technology: On-Chip and Off-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] R. D. (Shawn) Blanton , Subhasish Mitra Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. [Citation Graph (0, 0)][DBLP ] Conf ] Atul Jain , Anindya Saha , Jagdish Rao SoC Design Methodology: A Practical Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee , A. Keshavarzi , Amit Patra , Siddhartha Mukhopadhyay Test Methodologies in the Deep Submicron Era -- Analog, Mixed-Signal, and RF. [Citation Graph (0, 0)][DBLP ] Conf ] Dhiraj K. Pradhan , Magdy S. Abadir , Mauricio Varea Recent Advances in Verification, Equivalence Checking and SAT-Solvers. [Citation Graph (0, 0)][DBLP ] Conf ] A. B. Bhattacharyya Compact MOSFET Models for Low Power Analog CMOS Design. [Citation Graph (0, 0)][DBLP ] Conf ] D. Mukhopadhyay , P. K. Basu , V. R. Rao Physics and Technology: Towards Low-Power DSM Design. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Sandeep K. Shukla , Rajesh K. Gupta Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] C. L. (Dave) Liu The High Walls have Crumpled. [Citation Graph (0, 0)][DBLP ] Conf ] Ted Vucurevich 65nm Omnibudsman. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Naumann ESL - The Next Leadership Opportunity for India? [Citation Graph (0, 0)][DBLP ] Conf ] Shekhar Y. Borkar VLSI Design Challenges for Gigascale Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Walden C. Rhines Moore's Law is Unconstitutional. [Citation Graph (0, 0)][DBLP ] Conf ] Béatrice Fu Configurable Processor the Building Block for SOC (System-On-a-Chip). [Citation Graph (0, 0)][DBLP ] Conf ] Janick Bergeron Modeling Usable and Reusable Transactors in System Verilog. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian Optimizing SoC Manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Yan , Adit D. Singh A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Li , Krishnendu Chakrabarty , Seiji Kajihara , Shivakumar Swaminathan Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Huaxing Tang , Chen Wang , Janusz Rajski , Sudhakar M. Reddy , Jerzy Tyszer , Irith Pomeranz On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. [Citation Graph (0, 0)][DBLP ] Conf ] Loganathan Lingappan , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha , Srimat T. Chakradhar Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Biplab K. Sikdar , Sukanta Das , Samir Roy , Niloy Ganguly , Debesh K. Das Cellular Automata Based Test Structures with Logic Folding. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Lienig , Göran Jerke Electromigration-Aware Physical Design of Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shabbir H. Batterywala , Madhav P. Desai Variance Reduction in Monte Carlo Capacitance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Yibo Wang , Yici Cai , Xianlong Hong A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. [Citation Graph (0, 0)][DBLP ] Conf ] Venkat Rao , Gaurav Singhal , Anshul Kumar , Nicolas Navet Battery Model for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jorgen Peddersen , Seng Lin Shee , Andhi Janapsatya , Sri Parameswaran Rapid Embedded Hardware/Software System Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Haris Lekatsas , Jörg Henkel , Venkata Jakkula , Srimat T. Chakradhar A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Bhojwani , Rabi N. Mahapatra , Eun Jung Kim , Thomas Chen A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Narasimhan , Shantanu Divekar , Praveen Elakkumanan , Ramalingam Sridhar A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Theo Theocharides , Greg M. Link , Narayanan Vijaykrishnan , Mary Jane Irwin Implementing LDPC Decoding on Network-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Capewell , Ian Watson A RISC Hardware Platform for Low Power Java. [Citation Graph (0, 0)][DBLP ] Conf ] Sabyasachi Mondal , Arijit De , P. K. Biswas A Low Power Reprogrammable Parallel Processing VLSI Architecture for Computation of B-Spline Based Medical Image Processing System for Fast Characterization of Tiny Objects Suspended in Cellular Fluid. [Citation Graph (0, 0)][DBLP ] Conf ] Saraju P. Mohanty , N. Ranganathan , K. Balakrishnan Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. [Citation Graph (0, 0)][DBLP ] Conf ] Abdulkadir Utku Diril , Yuvraj Singh Dhillon , Abhijit Chatterjee , Adit D. Singh Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Shengqi Yang , Wayne Wolf , Narayanan Vijaykrishnan , Yuan Xie , Wenping Wang Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad Arsalan , Maitham Shams Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. S. Bhat , H. S. Jamadagni Power Optimization in Current Mode Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Malay K. Ganai , Pranav Ashar Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Kameshwar Chandrasekar , Michael S. Hsiao Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Tathagato Rai Dastidar , P. P. Chakrabarti A Verification System for Transient Response of Analog Circuits Using Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Sayantan Das , Ansuman Banerjee , Prasenjit Basu , Pallab Dasgupta , P. P. Chakrabarti , Chunduri Rama Mohan , Limor Fix Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] K. Uday Bhaskar , M. Prasanth , G. Chandramouli , V. Kamakoti A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Prasenjit Basu , Pallab Dasgupta , P. P. Chakrabarti Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnendu Chakrabarty Design, Testing, and Applications of Digital Microfluidics-Based Biochips. [Citation Graph (0, 0)][DBLP ] Conf ] Rui Zhang , Pallav Gupta , Niraj K. Jha Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. [Citation Graph (0, 0)][DBLP ] Conf ] C. Pramanik , T. Islam , H. Saha , J. Bhattacharya , S. Banerjee , Sagnik Dey Design, Fabrication, Testing and Simulation of Porous Silicon Based Smart MEMS Pressure Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin M. Irick , Wei Xu , Narayanan Vijaykrishnan , Mary Jane Irwin A Nanosensor Array-Based VLSI Gas Discriminator. [Citation Graph (0, 0)][DBLP ] Conf ] Avik Chakraborty Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Hafiz Md. Hasan Babu , Ahsan Raja Chowdhury Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Yuanzhong Wan , Maitham Shams Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoyong Tang , Tianyi Jiang , Alex K. Jones , Prithviraj Banerjee Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar Jain , M. Balakrishnan , Anshul Kumar Integrated On-Chip Storage Evaluation in ASIP Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Singh Saun , Preeti Ranjan Panda Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Achintya Halder , Soumendu Bhattacharya , Ganesh Srinivasan , Abhijit Chatterjee A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode. [Citation Graph (0, 0)][DBLP ] Conf ] Tejasvi Das , Clyde Washburn , P. R. Mukund , Steve Howard , Ken Paradis , Jung-Geau Jang , Jan Kolnik , Jeff Burleson Effects of Technology and Dimensional Scaling on Input Loss Prediction of RF MOSFETs. [Citation Graph (0, 0)][DBLP ] Conf ] Tin Wai Kwan , Maitham Shams Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Paul , Amit Patra , Shailendra Baranwal , Kaushik Dash Design of Second-Order Sub-Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Samiran Halder , Arindrajit Ghosh , Ravi Sankar Prasad , Anirban Chatterjee , Swapna Banerjee A 160MSPS 8-Bit Pipeline Based ADC. [Citation Graph (0, 0)][DBLP ] Conf ] Samiran Halder , Swapna Banerjee , Arindrajit Ghosh , Ravi Sankar Prasad , Anirban Chatterjee , Sanjoy Kumar Dey A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC. [Citation Graph (0, 0)][DBLP ] Conf ] Atul Katoch , Maurice Meijer , Sanjeev K. Jain Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Gaurav Kumar Varshney , Sreeram Chandrasekar An Efficient Methodology for Noise Characterization. [Citation Graph (0, 0)][DBLP ] Conf ] Sreeram Chandrasekar , V. Visvanathan , Gaurav Kumar Varshney Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sachin Shrivastava , Sreeram Chandrasekar Crosstalk Noise Analysis at Multiple Frequencies. [Citation Graph (0, 0)][DBLP ] Conf ] Jiaxing Sun , Yun Zheng , Qing Ye , Tianchun Ye Worst-Case Crosstalk Noise Analysis Based on Dual-Exponential Noise Metrics. [Citation Graph (0, 0)][DBLP ] Conf ] Ajoy Kumar Palit , Volker Meyer , Walter Anheier , Jürgen Schlöffel ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Vishak Venkatraman , Wayne Burleson Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] C. Brej , Jim D. Garside A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Yuh-Fang Tsai , Narayanan Vijaykrishnan , Yuan Xie , Mary Jane Irwin Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. [Citation Graph (0, 0)][DBLP ] Conf ] Baohua Wang , Pinaki Mazumder Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion. [Citation Graph (0, 0)][DBLP ] Conf ] A. Madan , S. C. Bose , P. J. George , Chandra Shekhar Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs. [Citation Graph (0, 0)][DBLP ] Conf ] R. Srinivasan , Navakanta Bhat Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Hoffmann , Frank Fiedler , Achim Nohl , Surender Parupalli A Methodology and Tooling Enabling Application Specific Processor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Debdeep Mukhopadhyay , Dipanwita Roy Chowdhury An Efficient End to End Design of Rijndael Cryptosystem in 0.18 ? CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Gaurav Arora , Abhishek Sharma , D. Nagchoudhuri , M. Balakrishnan ADOPT: An Approach to Activity Based Delay Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasa R. Sridhara , Naresh R. Shanbhag Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Jeng-Liang Tsai , Dong Hyun Baik , Charlie Chung-Ping Chen , Kewal K. Saluja False Path and Clock Scheduling Based Yield-Aware Gate Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] R. Gopalakrishnan , Rajat Moona Variable Resizing for Area Improvement in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Eschbach , Wolfgang Günther , Bernd Becker Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Garg , Laurent Le Cam , Matthieu Gonzalez Lithography Driven Layout Design. [Citation Graph (0, 0)][DBLP ] Conf ] Edward Hursey , Nikhil Jayakumar , Sunil P. Khatri Non-Manhattan Routing Using a Manhattan Router. [Citation Graph (0, 0)][DBLP ] Conf ] R. Manimegalai , E. Siva Soumya , V. Muralidharan , Balaraman Ravindran , V. Kamakoti , D. Bhatia Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Roy Hartono , Nuttorn Jangkrajarng , Sambuddha Bhattacharya , C.-J. Richard Shi Automatic Device Layout Generation for Analog Layout Retargeting. [Citation Graph (0, 0)][DBLP ] Conf ] Suvodeep Gupta , Srinivas Katkoori , Hariharan Sankaran Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Li , Seongmoon Wang , Srimat T. Chakradhar , Sudhakar M. Reddy Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Aniket , Ravishankar Arunachalam Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Gopalan , Tejasvi Das , Clyde Washburn , P. R. Mukund An Ultra-Fast, On-Chip BiST for RF Low Noise Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Sheng Zhang , Sharad C. Seth , Bhargab B. Bhattacharya On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , R. Dandamudi , V. R. Devanathan , N. Haldar , K. Kiran , P. S. Vijay Kumar A Framework for Distributed and Hierarchical Design-for-Test. [Citation Graph (0, 0)][DBLP ] Conf ] P. Kalpana , K. Gunavathi A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets. [Citation Graph (0, 0)][DBLP ] Conf ] Falguni Bala , Tapas Nandy Conventional RC oscillators, though offer inexpensiveProgrammable High Frequency RC Oscillator. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring Oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Ashis Maity , R. G. Raghavendra , Pradip Mandal On-Chip Voltage Regulator with Improved Transient Response. [Citation Graph (0, 0)][DBLP ] Conf ] Mengmeng Ding , Ranga Vemuri An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. [Citation Graph (0, 0)][DBLP ] Conf ] Abhishek Somani , P. P. Chakrabarti , Amit Patra A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Jen Yen , Wen-Yaw Chung , Mely Chen Chi A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch. [Citation Graph (0, 0)][DBLP ] Conf ] Dipankar Das , Rajeev Kumar , P. P. Chakrabarti Dictionary Based Code Compression for Variable Length Instruction Encodings. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Sun , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Andrei Terechko , Manish Garg , Henk Corporaal Evaluation of Speed and Area of Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Nagendran Rangan , Karam S. Chatha A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushal R. Gandhi , Nihar R. Mahapatra Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Bansal , Kanishka Lahiri , Anand Raghunathan , Srimat T. Chakradhar Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjukta Bhanja , Karthikeyan Lingasubramanian , N. Ranganathan Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jiangjiang Liu , Krishnan Sundaresan , Nihar R. Mahapatra Energy-Efficient Compressed Address Transmission. [Citation Graph (0, 0)][DBLP ] Conf ] Tezaswi Raja , Vishwani D. Agrawal , Michael L. Bushnell Variable Input Delay CMOS Logic for Low Power Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ankur Goel , Baquer Mazhari Gate Leakage and Its Reduction in Deep Submicron SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Parthasarathi Dasgupta Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Srinivasan , Karam S. Chatha ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Dharmendra Saraswat , Ramachandra Achar , Michel S. Nakhla Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Narasimhan , Manish Kasotiya , Ramalingam Sridhar A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Denis Deschacht , Alain Lopez Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation. [Citation Graph (0, 0)][DBLP ] Conf ] Madhubanti Mukherjee , Ranga Vemuri On Physical-Aware Synthesis of Vertically Integrated 3D Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Anup Hosangadi , Farzan Fallah , Ryan Kastner Energy Efficient Hardware Synthesis of Polynomial Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] C. H. Wang , Ahmet T. Erdogan , Tughrul Arslan Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Renqiu Huang , Ranga Vemuri On-Line Synthesis for Partially Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Chattopadhyay , Manas Kumar Dewangan A Combinational Logic Mapper for Actel's SX/AX Family. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Prasad Raghuraman , Haibo Wang , Spyros Tragoudas A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan , Sani R. Nassif Power Variability and Its Impact on Design. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Sundaresan , Nihar R. Mahapatra An Accurate Energy and Thermal Model for Global Signal Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Subhashis Majumder , Susmita Sur-Kolay , Subhas C. Nandy , Bhargab B. Bhattacharya , B. Chakraborty Hot Spots and Zones in a Chip: A Geometrician's View. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv V. Joshi , S. S. Kang , N. Zamdmar , A. Mocuta , Ching-Te Chuang , J. A. Pascual-Gutiérrez Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Raghvendra , Philippe Hurat DFM: Linking Design and Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , William R. Hunter , Poras T. Balsara , Cyrus Cantrell The Impact of Inductance on Transients Affecting Gate Oxide Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Thara Rejimon , Sanjukta Bhanja An Accurate Probalistic Model for Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Kunal K. Dave , Vishwani D. Agrawal , Michael L. Bushnell Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. [Citation Graph (0, 0)][DBLP ] Conf ] Deepali Koppad , Alexandre V. Bystrov , Alexandre Yakovlev Off-Line Testing of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] E. Syam Sundar Reddy , Vikram Chandrasekhar , Milagros Sashikánth , V. Kamakoti , Narayanan Vijaykrishnan Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh Goyal , Mihir R. Choudhury , S. S. S. P. Rao , L. Kalyan Kumar Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Zahid Khan , Tughrul Arslan , Ahmet T. Erdogan A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems. [Citation Graph (0, 0)][DBLP ] Conf ] G. N. Nandakumar , Nirav Patel , Raghunatha Reddy , Makeshwar Kothandaraman Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Reza Ghasemi , Zainalabedin Navabi An Effective VHDL-AMS Simulation Algorithm with Event Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] B. Suresh , V. Visvanathan , R. S. Krishnan , H. S. Jamadagni Application of Alpha Power Law Models to PLL Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor Pering , Vijay Raghunathan , Roy Want Exploiting Radio Hierarchies for Power-Efficient Wireless Device Discovery and Connection Setup. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh Kumar Singh , T. K. Bhattacharyya , Ashudeb Dutta Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Shibaji Banerjee , Debdeep Mukhopadhyay , Dipanwita Roy Chowdhury Computer Aided Test (CAT) Tool for Mixed Signal SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] G. Josemin Bala , J. Raja Paul Perinbam A Novel Low Power 16X16 Content Addressable Memory Using PA. [Citation Graph (0, 0)][DBLP ] Conf ] Chakka Siva Sai Prasanna , N. Sudha , V. Kamakoti A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Nitin Gupta , Doug A. Edwards Synthesis of Asynchronous Circuits Using Early Data Validity. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan Bahukudumbi , Krishna Bharath A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Sankar P. Debnath , Jairam Sukumar , H. Udaykumar A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo Romero , Gabriela Peretti , Carlos A. Marqués An Operational Amplifier Model for Test Planning at Behavioral Level. [Citation Graph (0, 0)][DBLP ] Conf ] Aleksandar Beric , Ramanathan Sethuraman , Jef L. van Meerbergen , Gerard de Haan Memory-Centric Motion Estimator. [Citation Graph (0, 0)][DBLP ] Conf ] Marong Phadoongsidhi , Kewal K. Saluja SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Shiang Lin , Dennis Sylvester A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Mukul Milind Ojha , Arun Kumar Anand , G. S. Visweswaran , D. Nagchoudhuri A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Murthy Durbhakula Applicability of General Purpose Processors to Network Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ramaprasath Vilangudipitchai , Poras T. Balsara Power Switch Network Design for MTCMOS. [Citation Graph (0, 0)][DBLP ] Conf ] AdityaSankar Medury , Ingvar Carlson , Atila Alvandpour , John Stensby Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Aliakbar Ghadiri , Hamid Mahmoodi-Meimand Dual-Edge Triggered Static Pulsed Flip-Flops. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Dutta , Wouter A. Serdijn , Swapna Banerjee , Sriram Gupta A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Lian-xi Liu , Yin-tang Yang , Zhang-ming Zhu A High Accuracy Bandgap Reference with Chopped Modulator to Compensate MOSFET Mismatch. [Citation Graph (0, 0)][DBLP ] Conf ] Biranchinath Sahu , Gabriel A. Rincón-Mora A High-Efficiency, Dual-Mode, Dynamic, Buck-Boost Power Supply IC for Portable Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Arindam Basu , Anindya Sundar Dhar Design Issues in Switched Capacitor Ladder Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Shubhajit Roy Chowdhury , C. Pramanik , H. Saha ASIC Design of the Linearisation Circuit of a PTC Thermistor. [Citation Graph (0, 0)][DBLP ] Conf ] Tien-Ling Hsieh , Ranjit Gharpurey A Reconfigurable Oscillator Topology for Dual-Band Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Sill , Frank Grassert , Dirk Timmermann Reducing Leakage with Mixed-V_th (MVT). [Citation Graph (0, 0)][DBLP ] Conf ] Ghanshyam Nayak , Clyde Washburn , P. R. Mukund System in a Package Design of a RF Front End System Using Application Specific Reduced Order Models. [Citation Graph (0, 0)][DBLP ] Conf ] 