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Conferences in DBLP

VLSI Design (vlsid)
1995 (conf/vlsid/1995)

  1. Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani
    Optimal algorithms for planar over-the-cell routing in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:3-7 [Conf]
  2. Andrew Lim, Sartaj K. Sahni, Venkat Thanvantri
    A fast algorithm to test planar topological routability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:8-12 [Conf]
  3. S. Das, Sanjeev Saxena
    Parallel algorithms for single row routing in narrow streets. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:13-18 [Conf]
  4. Raj S. Mitra, Mahmood G. Qadir, Anupam Basu
    A consistent labeling approach to hardware software partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:19-24 [Conf]
  5. Anoop Singhal, Chi-Yuan Lo
    Object oriented data modeling for VLSI/CAD. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:25-29 [Conf]
  6. Raj S. Mitra, Partha S. Roop, Anupam Basu
    Implementation of design functions by available devices: a new algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:30-35 [Conf]
  7. James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
    An asynchronous algorithm for sequential circuit test generation on a network of workstations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:36-41 [Conf]
  8. Tapan J. Chakraborty, Vishwani D. Agrawal
    Robust testing for stuck-at faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:42-46 [Conf]
  9. Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal
    Functional test generation for non-scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:47-52 [Conf]
  10. Suthikshn Kumar, Kevin E. Forward, M. Palaniswami
    A fast-multiplier generator for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:53-56 [Conf]
  11. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
    Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:57-62 [Conf]
  12. A. Pal, R. K. Gorai, V. V. S. S. Raju
    Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:63-68 [Conf]
  13. Mahesh Mehendale, M. K. Ram Prasad
    AATMA: an algorithm for technology mapping for antifuse-based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:69-74 [Conf]
  14. Alok Kumar, Anshul Kumar, M. Balakrishnan
    Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:75-80 [Conf]
  15. Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross
    Efficient variable ordering and partial representation algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:81-86 [Conf]
  16. Santonu Sarkar, Anupam Basu, Arun K. Majumdar
    Synchronization of communicating modules and processes in high level synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:87-92 [Conf]
  17. Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Functional clock schedule optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:93-98 [Conf]
  18. Xinghao Chen, Michael L. Bushnell
    Generation of search state equivalence for automatic test pattern generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:99-103 [Conf]
  19. Anand Raghunathan, Pranav Ashar, Sharad Malik
    Test generation for cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:104-109 [Conf]
  20. Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy
    MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:110-115 [Conf]
  21. S. Venkatraman, Sharad C. Seth, Prathima Agrawal
    Parallel test generation with low communication overhead. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:116-120 [Conf]
  22. U. K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta
    PLA based synthesis and testing of hazard free logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:121-124 [Conf]
  23. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A new switching-level approach to multiple-output functions synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:125-129 [Conf]
  24. Sven Simon, Ralf Bucher, Josef A. Nossek
    Retiming of synchronous circuits with variable topology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:130-134 [Conf]
  25. Srimat T. Chakradhar
    Optimum retiming of large sequential circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:135-140 [Conf]
  26. Priyadarsan Patra, Donald S. Fussell
    Fully asynchronous, robust, high-throughput arithmetic structures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:141-145 [Conf]
  27. Ali Skaf, Alain Guyot
    SAGA: the first general-purpose on-line arithmetic co-processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:146-149 [Conf]
  28. S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta
    A single chip, pipelined, cascadable, multichannel, signal processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:150-155 [Conf]
  29. Luca Penzo, Donatella Sciuto, Cristina Silvano
    VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:156-160 [Conf]
  30. Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
    An efficient automatic test generation system for path delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:161-165 [Conf]
  31. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
    Statistical methods for delay fault coverage analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:166-170 [Conf]
  32. Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:171-176 [Conf]
  33. Imtiaz P. Shaik, Michael L. Bushnell
    A graph approach to DFT hardware placement for robust delay fault BIST. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:177-182 [Conf]
  34. P. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar
    A highly testable ASIC for telephone signaling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:183-0 [Conf]
  35. Debabrata Ghosh, Soumitra Kumar Nandy
    Wave pipelined architecture folding: a method to achieve low power and low area. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:184-0 [Conf]
  36. Goutam Debnath, K. Debnath, R. Fernando
    The Pentium processor-90/100, microarchitecture and low power circuit design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:185-190 [Conf]
  37. Puneet Sawhney, Haroon Rasheed
    Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:191-0 [Conf]
  38. Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh
    A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:192-0 [Conf]
  39. Nagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana
    CODAC-a characterization system for digital and analog circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:193-0 [Conf]
  40. Hameed A. Naseem, Ajay P. Malshe, Rajan A. Beera, M. Shahid Haque, William D. Brown, Len W. Schaper
    CVD-diamond substrates for multi-chip modules (MCMs). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:194-0 [Conf]
  41. Rajat K. Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal
    Computing area and wire length efficient routes for channels. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:196-201 [Conf]
  42. Rajat K. Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal
    A general graph theoretic framework for multi-layer channel routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:202-207 [Conf]
  43. Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar
    Testability-oriented channel routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:208-213 [Conf]
  44. Hossein Sahabi, Anup Basu, Mark Fiala
    VLSI implementation of variable resolution image compression. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:214-219 [Conf]
  45. Mario Kovac, N. Ranganathan
    JAGUAR: a high speed VLSI chip for JPEG image compression standard. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:220-224 [Conf]
  46. Jacob Augustine, Wen Feng, James Jacob
    Logic minimization based approach for compressing image data. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:225-228 [Conf]
  47. Anirudh Devgan, Ronald A. Rohrer
    Efficient simulation of interconnect and mixed analog-digital circuits in ACES. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:229-233 [Conf]
  48. Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
    Efficient multisine testing of analog circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:234-238 [Conf]
  49. A. K. B. A'ain, A. H. Bratt, A. P. Dorey
    Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:239-242 [Conf]
  50. William L. Bradley, Ranga Vemuri
    Transformations for functional verification of synthesized designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:243-248 [Conf]
  51. B. M. Subraya, Anshul Kumar, Shashi Kumar
    An HOL based framework for design of correct high level synthesizers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:249-254 [Conf]
  52. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    Formal synthesis of circuits with a simple handshake protocol. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:255-259 [Conf]
  53. S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy
    Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:260-263 [Conf]
  54. D. V. Das
    EM simulation [ICs and MCMs]. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:264-267 [Conf]
  55. G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee
    Analysis of temperature dependence of Si-Ge HBT. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:268-271 [Conf]
  56. C. P. Ravikumar, Hemant Joshi
    HISCOAP: a hierarchical testability analysis tool. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:272-277 [Conf]
  57. S. M. Aziz
    A C-testable modified Booth's array multiplier. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:278-282 [Conf]
  58. Arun Balakrishnan, Srimat T. Chakradhar
    Partial scan design for technology mapped circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:283-287 [Conf]
  59. Elizabeth M. Rudnick, Janak H. Patel
    A genetic approach to test application time reduction for full scan and partial scan circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:288-293 [Conf]
  60. Manjit Borah, Mary Jane Irwin, Robert Michael Owens
    Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:294-298 [Conf]
  61. Vincenzo Catania, Marco Russo
    Analog gates for a VLSI fuzzy processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:299-304 [Conf]
  62. S. C. Prasad, Kaushik Roy
    Circuit optimization for minimisation of power consumption under delay constraint. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:305-309 [Conf]
  63. George A. Hadgis, P. R. Mukund
    A novel CMOS monolithic analog multiplier with wide input dynamic range. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:310-314 [Conf]
  64. Giuseppe Ascia, Vincenzo Catania
    Design of a VLSI parallel processor for fuzzy computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:315-320 [Conf]
  65. Lizy Kurian John, Daniel Brewer, Eugene John
    Design of a highly reconfigurable interconnect for array processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:321-325 [Conf]
  66. Meenakshisundaram Gopi, Swami Manohar
    A VLSI architecture for the computation of NURBS patches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:326-331 [Conf]
  67. V. Visvanathan, S. Ramanathan
    A modular systolic architecture for delayed least mean squares adaptive filtering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:332-337 [Conf]
  68. Sreejit Chakravarty, Yiming Gong
    Voting model based diagnosis of bridging faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:338-342 [Conf]
  69. Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
    Board level fault diagnosis using cellular automata array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:343-348 [Conf]
  70. Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen
    An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:349-354 [Conf]
  71. B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh
    A new methodology for the design of low-cost fail safe circuits and networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:355-358 [Conf]
  72. Jin-Tai Yan, Pei-Yung Hsiao
    A new fuzzy-clustering-based approach for two-way circuit partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:359-364 [Conf]
  73. Khushro Shahookar, Pinaki Mazumder
    Genetic multiway partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:365-369 [Conf]
  74. P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya
    VLSI floorplan generation and area optimization using AND-OR graph search. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:370-375 [Conf]
  75. Dinesh Bhatia, James Haralambides
    Resource requirements for field programmable interconnection chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:376-380 [Conf]
  76. Luis A. Montalvo, Alain Guyot
    Svoboda-Tung division with no compensation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:381-385 [Conf]
  77. Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, N. Vaucher
    Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:386-391 [Conf]
  78. D. V. Poornaiah, P. V. Ananda Mohan
    Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:392-397 [Conf]
  79. W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi
    A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:398-402 [Conf]
  80. Sunil R. Das, H. T. Ho, Wen-Ben Jone, A. R. Nayak
    An improved output compaction technique for built-in self-test in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:403-407 [Conf]
  81. Chunduri Rama Mohan, Partha Pratim Chakrabarti
    Combined optimization of area and testability during state assignment of PLA-based FSM's. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:408-413 [Conf]
  82. Manoj Franklin, Kewal K. Saluja, Kyuchull Kim
    Fast computation of MISR signatures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:414-418 [Conf]
  83. Jason P. Hurst, Adit D. Singh
    A differential built-in current sensor design for high speed IDDQ testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:419-423 [Conf]
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