Conferences in DBLP
Bapiraju Vinnakota , Ramesh Harjani Mixed-Signal Design for Test. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , R. K. Roy Low Power Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer , Sharad Malik Register Transfer Level Synthesis: From Theory to Practice. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Gupta Hardware Software Co-Design of Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] A. Ratan Gupta , V. Visvanathan VLSI Implementation of DSP Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob A. Abraham , Gopi Ganapathy Practical Test and DFT for Next Generation VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal Science, Technology, and the Indian Society. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas J. Engibou The New Electronics Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Brodersen , Rajeev Jain VLSI in Mobile Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Mani B. Srivastava Medium access control and air-interface subsystem for an indoor wireless ATM network. [Citation Graph (0, 0)][DBLP ] Conf ] A. Sriram , Fadi J. Kurdahi Behavioral Modeling of an ATM Switch using SpecCharts. [Citation Graph (0, 0)][DBLP ] Conf ] Bengt Svantesson , Ahmed Hemani , Peeter Ellervee , Adam Postula , Johnny Öberg , Axel Jantsch , Hannu Tenhunen A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. [Citation Graph (0, 0)][DBLP ] Conf ] Chetana Nagendra , Robert Michael Owens , Mary Jane Irwin Design tradeoffs in high speed multipliers and FIR filters. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Tai Yan A simple yet effective genetic approach for the orientation assignment on cell-based layout. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Chandy , Prithviraj Banerjee Parallel simulated annealing strategies for VLSI cell placement. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Das , Bhargab B. Bhattacharya Channel routing in Manhattan-diagonal model. [Citation Graph (0, 0)][DBLP ] Conf ] Si-Qing Zheng , Joon Shik Lim , S. Sitharama Iyengar Routing using implicit connection graphs [VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] Tapan J. Chakraborty , Vishwani D. Agrawal Design for high-speed testability of stuck-at faults. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed Fadle Abdulla , C. P. Ravikumar , Anshul Kumar A Novel BIST Architecture With Built-in Self Check. [Citation Graph (0, 0)][DBLP ] Conf ] S. Nandi , Santanu Chattopadhyay , Parimal Pal Chaudhuri Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Koppolu Sasidhar , Abhijit Chatterjee Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates. [Citation Graph (0, 0)][DBLP ] Conf ] D. V. Poornaiah , P. V. Ananda Mohan A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. [Citation Graph (0, 0)][DBLP ] Conf ] J. Shu , Thomas Charles Wilson , Dilip K. Banerji Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Leupers , Peter Marwedel Instruction-Set Modeling for ASIP Code Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Jürgen Becker , Rainer Kress , Helmut Reinig CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. [Citation Graph (0, 0)][DBLP ] Conf ] A. B. Bhattacharyya , R. S. Rana , S. K. Guha , Rajendar Bahl , R. Anand , M. J. Zarabi , P. A. Govindacharyulu , U. Gupta , V. Mohan , Jatin Roy , Amul Atri A micropower analog hearing aid on low voltage CMOS digital process. [Citation Graph (0, 0)][DBLP ] Conf ] C. Srinivasan , K. Radhakrishna Rao A 20MHz CMOS Variable Gain Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Boni , Carlo Morandi Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation. [Citation Graph (0, 0)][DBLP ] Conf ] J. Weiss , B. Majoux , G. Bouvier A Very High Gain Bandwidth Product Fully Differential Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Paul J. Thadikaran , Sreejit Chakravarty Fast Algorithms for Computer IDDQ Tests for Combination Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Jawahar Jain , Masahiro Fujita , Jacob A. Abraham , Donald S. Fussell On More Efficient Combinational ATPG Using Functional Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Balakrishnan , Srimat T. Chakradhar Sequential Circuits with combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Rajamani Rajarajan Genetic Algorithms for Scan Path Design. [Citation Graph (0, 0)][DBLP ] Conf ] Chittaranjan A. Mandal , P. P. Chakrabarti , Sujoy Ghose Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Katkoori , Ranga Vemuri , Jay Roy A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Johnny Öberg , Jouni Isoaho , Peeter Ellervee , Axel Jantsch , Ahmed Hemani A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. [Citation Graph (0, 0)][DBLP ] Conf ] Santonu Sarkar , Anupam Basu , Arun K. Majumdar Representation and Synthesis of Interface of a Circuit for its Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Natesan Venkateswaran , Dinesh Bhatia Clock-Skew Constrained Cell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Rohini Gupta , Byron Krauter , Lawrence T. Pileggi On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] R. P. Suresh , P. Venugopal , S. Tamizh Selvam , S. Potla Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. [Citation Graph (0, 0)][DBLP ] Conf ] Yinghua Min , Zhuxing Zhao , Zhongcheng Li An Analytical Delay Model Based on Boolean Process. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy John Lambert , Kewal K. Saluja Methods for Dynamic Test Vector compaction in Sequential Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Raghunathan , Srimat T. Chakradhar Dynamic test Sequence compaction for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dhruva R. Chakrabarti , Ajai Jain An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Savita Banerjee , Srimat T. Chakradhar , Rabindra K. Roy Synchronous Test Generation Model for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof Bilinski , Erik L. Dagless , Jonathan M. Saul Behavioral Synthesis of Complex Parallel Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Raghava V. Cherabuddi , Jijun Chen , Magdy A. Bayoumi A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Naren Narasimhan , Ranga Vemuri , Jay Roy Synchronous Controller Models for Synthesis from Communicating VHDL Processes. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , V. Saxena Synthesis of Testable Pipelined Datapaths Using Genetic Search. [Citation Graph (0, 0)][DBLP ] Conf ] A. Singla , T. M. Conte Bipartitioning for Hybrid FPGA-Software Simulatio. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Suyama , Hiroshi Sawada , Akira Nagoya LUT-based FPGA Technology Mapping using Permissible Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Lizy Kurian John VaWiRAM: a variable width random access memory module. [Citation Graph (0, 0)][DBLP ] Conf ] Fran Hanchek , Shantanu Dutt Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee , Bruce C. Kim , Naveena Nagi Low-cost DC built-in self-test of linear analog circuits using checksums. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip Mandal , V. Visvanathan Design of high performance two stage CMOS cascode op-amps with stable biasing. [Citation Graph (0, 0)][DBLP ] Conf ] A. K. B. A'ain , A. H. Bratt , A. P. Dorey Testing Analogue Circuits by A C Power Supply Voltage. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Ramadoss , Michael L. Bushnell Test generation for mixed-signal devices using signal flow graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Narayan , Sunil P. Khatri , Jawahar Jain , Masahiro Fujita , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli A study of composition schemes for mixed apply/compose based construction of ROBDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Debesh Kumar Das , Bhargab B. Bhattacharya Does retiming affect redundancy in sequential circuits? [Citation Graph (0, 0)][DBLP ] Conf ] Nripendra N. Biswas , C. Srikanth , James Jacob Cubical CAMP for minimization of Boolean functions. [Citation Graph (0, 0)][DBLP ] Conf ] S. Bhattacharjee , J. Bhattacharya , U. Raghavendra , Debashis Saha , Parimal Pal Chaudhuri A VLSI architecture for cellular automata based parallel data compression. [Citation Graph (0, 0)][DBLP ] Conf ] M. P. Sebastian , P. S. Nagendra Rao , Lawrence Jenkins VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Krishna , Abdel Ejnioui , N. Ranganathan A tree matching chip. [Citation Graph (0, 0)][DBLP ] Conf ] S. Ramanathan , V. Visvanathan A systolic architecture for LMS adaptive filtering with minimal adaptation delay. [Citation Graph (0, 0)][DBLP ] Conf ] Lakshminarayana Pappu , Michael L. Bushnell , Vishwani D. Agrawal , Mandyam-Komar Srinivas Statistical path delay fault coverage estimation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Balakrishnan , Srimat T. Chakradhar Retiming with logic duplication transformation: theory and an application to partial scan. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Maurer Is Compiled Simulation Really Faster than Interpreted Simulation? [Citation Graph (0, 0)][DBLP ] Conf ] S. Sundaram , Lalit M. Patnaik Distributed logic simulation: time-first evaluation vs. event driven algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] S. Samel , Bert Gyselinckx , Ivo Bolsens , Hugo De Man Designing Systems On Silicon: A Digital Spread Spectrum Pager. [Citation Graph (0, 0)][DBLP ] Conf ] Shriram Kulkarni , Pinaki Mazumder , George I. Haddad A high-speed 32-bit parallel correlator for spread spectrum communication. [Citation Graph (0, 0)][DBLP ] Conf ] S. Mitra , S. Das , Parimal Pal Chaudhuri , S. Nandi Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins. [Citation Graph (0, 0)][DBLP ] Conf ] Ranjeet Ranade , Sanjay Bhandari , A. N. Chandorkar VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Chattopadhyay , S. Mitra , Parimal Pal Chaudhuri Cellular automata based architecture of a database query processor. [Citation Graph (0, 0)][DBLP ] Conf ] Jaswinder Pal Singh , A. Kumar , Sanjeev Kumar A multiplier generator for Xilinx FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Mukul R. Prasad , Lavmeet S. Hora Estimation of Power from Module-level Netlists. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Tiwari , Sharad Malik , Andrew Wolfe , Mike Tien-Chien Lee Instruction Level Power Analysis and Optimization of Software. [Citation Graph (0, 0)][DBLP ] Conf ] Suresh Rajgopal Challenges in Low Power Microprocessor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhir Aggarwal An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] S. K. Gupta , M. M. Hasan KANSYS: a CAD tool for analog circuit synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] G. Enrique Fernandez , R. Sridhar Dual rail static CMOS architecture for wave pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil R. Das , N. Goel , Wen-Ben Jone , A. R. Nayak Syndrome signature in output compaction for VLSI BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Arunita Jaekel , Graham A. Jullien , Subir Bandyopadhyay Multilevel Factorization Technique for Pass Transistor Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , David Lee Characteristic polynomial method for verification and test of combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Narayanan Vijaykrishnan , N. Ranganathan SUBGEN: a genetic approach for subcircuit extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Jatan C. Shah , Sachin S. Sapatnekar Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. [Citation Graph (0, 0)][DBLP ] Conf ] Anantha Chandrakasan Ultra low power digital signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Navin Chaddha , Mohan Vishwanath A low power video encoder with power, memory and bandwidth scalability. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan-Yu Wang , Kaushik Roy Maximum power estimation for CMOS circuits using deterministic and statistic approaches. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , Sunil D. Sherlekar , G. Venkatesh Low power realization of FIR filters using multirate architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Guyot , Marc Renaudin , Bachar El Hassan , Volker Levering Self timed division and square-root extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Radhakrishna Nagalla , Graham R. Hellestrand Elimination of Dynamic Hazards from Signal Transition Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Bum Park , Takashi Nanya Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Prathima Agrawal , B. Narendran , Narayanan Shivakumar Multi-way partitioning of VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Parthasarathi Dasgupta , A. K. Sen , Subhas C. Nandy , Bhargab B. Bhattacharya Geometric bipartitioning problem and its applications to VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Identifying Redundant Path Delay Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mukund Sivaraman , Andrzej J. Strojwas Diagnosis of parametric path delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Ananta K. Majhi , James Jacob , Lalit M. Patnaik , Vishwani D. Agrawal On test coverage of path delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal Improving accuracy in path delay fault coverage estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Marwan A. Gharaybeh , Michael L. Bushnell , Vishwani D. Agrawal Parallel concurrent path-delay fault simulation using single-input change patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Anantha Chandrakasan , Kurt Keutzer , A. Khandekar , S. L. Maskara , B. D. Pradhan , Mani B. Srivastava Mobile Communications: Demands on VLSI Technology, Design and CAD. [Citation Graph (0, 0)][DBLP ] Conf ] 