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Conferences in DBLP

VLSI Design (vlsid)
1997 (conf/vlsid/1997)

  1. K. R. Rao, Magdy A. Bayoumi, T. V. Subramaniam
    T1: Multimedia. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:2-0 [Conf]
  2. P. A. Subrahmanyam, R. Gupta, B. S. Rao
    T2: HW-SW Codesign. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:2-0 [Conf]
  3. Dinesh P. Mehta, Naveed A. Sherwani, A. Bariya
    T3: Physical Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:3-0 [Conf]
  4. K. Roy, R. Roy, Ramesh Harjani, K. S. Murthy
    T5: Low-Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:4-0 [Conf]
  5. P. Meyer
    T6: C++/java(Tm)/unix. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:4-0 [Conf]
  6. Kamran Eshraghian
    Opto-VLSI Systems for Multimedia Computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:6-9 [Conf]
  7. P. Mazumdar
    Parallel VLSI-Routing Models for Polymorphic Processors Array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:10-14 [Conf]
  8. Avaneendra Gupta, John P. Hayes
    A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:15-20 [Conf]
  9. Jianzhong Shi, Akash Randhar, Dinesh Bhatia
    Macro Block Based FPGA Floorplanning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:21-26 [Conf]
  10. Jens Lienig
    Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:27-31 [Conf]
  11. Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan
    A New Partitioning Strategy Based on Supermodular Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:32-37 [Conf]
  12. R. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik
    Effective Heuristics for Timing Driven Constructive Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:38-45 [Conf]
  13. Bernd Becker, Rolf Drechsler
    Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:46-50 [Conf]
  14. Gary William Grewal, Thomas Charles Wilson
    An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:51-56 [Conf]
  15. Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao
    A Technology Mapper for Xilinx FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:57-61 [Conf]
  16. Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar
    Rapid Synthesis of Multi-Chip Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:62-68 [Conf]
  17. Gagan Hasteer, Prithviraj Banerjee
    Simulated Annealing Based Parallel State Assignment of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:69-75 [Conf]
  18. Montek Singh, Steven M. Nowick
    Synthesis for Logical Initializability of Synchronous Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:76-81 [Conf]
  19. Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
    A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:82-87 [Conf]
  20. Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal
    Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:88-94 [Conf]
  21. Mukund Sivaraman, Andrzej J. Strojwas
    Primitive Path Delay Fault Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:95-100 [Conf]
  22. Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy
    (Quasi-) Linear Path Delay Fault Tests for Adders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:101-105 [Conf]
  23. Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
    Delay Fault Coverage Enhancement Using Multiple Test Observation Times. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:106-110 [Conf]
  24. A. Dharchoudhuri, S. M. Kang
    Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:111-117 [Conf]
  25. C. P. Ravikumar, R. Aggarwal, C. Sharma
    A Graph-Theoretic Approach for Register File Based Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:118-123 [Conf]
  26. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:124-129 [Conf]
  27. Heman Khanna, M. Balakrishnan
    Allocation of FIFO Structures in RTL Data Paths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:130-133 [Conf]
  28. A. R. Naseer, M. Balakrishnan, Anshul Kumar
    Optimal Clock Period for Synthesized Data Paths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:134-139 [Conf]
  29. Madhavi Vootukuru, Ranga Vemuri, Nand Kumar
    Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:140-145 [Conf]
  30. Reiner W. Hartenstein, Jürgen Becker
    Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:146-150 [Conf]
  31. Santonu Sarkar, Anupam Basu, Arun K. Majumdar
    Analyzing Controllability of a Hardware Circuit for its Reuse. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:151-154 [Conf]
  32. Debanjan Saha, Anupam Basu, Raj S. Mitra
    Hardware Software Partitioning Using Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:155-160 [Conf]
  33. José M. Mendías, Román Hermida, Milagros Fernández
    Formal Techniques for Hardware Allocation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:161-165 [Conf]
  34. Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
    Design Space Exploration for Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:166-173 [Conf]
  35. Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
    Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:174-178 [Conf]
  36. P. Patil, Tan-Li Chou, Kaushik Roy, R. Roy
    Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:179-184 [Conf]
  37. Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez
    Dynamic Power Management for Microprocessors: A Case Study. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:185-192 [Conf]
  38. Vishwani D. Agrawal
    Low-Power Design by Hazard Filtering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:193-197 [Conf]
  39. S. Ramanathan, V. Visvanathan
    Low-Power Configurable Processor Array for DLMS Adaptive Filtering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:198-207 [Conf]
  40. S. P. Rajan, Natarajan Shankar, Mandayam K. Srivas
    Industrial Strength Formal Verification Techniques for Hardware Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:208-212 [Conf]
  41. Gitanjali Swamy
    Formal Verification of Digital Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:213-217 [Conf]
  42. Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    Formal Verification of Combinational Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:218-225 [Conf]
  43. I. Chakrabarti, Dilip Sarkar, Arun K. Majumdar
    Inductive Verification of Sequential Circuits with a Datapath. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:226-231 [Conf]
  44. Rajeev Murgai, Masahiro Fujita
    Some Recent Advances in Software and Hardware Logic Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:232-238 [Conf]
  45. S. Harikumer, S. Kumar
    Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:239-243 [Conf]
  46. Sunil Nanda
    Media Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:244-246 [Conf]
  47. Partha Sarathi Bhattacharjee, Sajal K. Das, Debashis Saha, D. Roychowdhury, Parimal Pal Chaudhuri
    A Parallel Architecture for Video Compression. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:247-252 [Conf]
  48. Giuseppe Ascia, Vincenzo Catania, Giuseppe Ficili
    Design of a VLSI Hardware PET Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:253-256 [Conf]
  49. Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An
    A Scalable Memory System Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:257-260 [Conf]
  50. Milind B. Kamble, Kanad Ghose
    Energy-Efficiency of VLSI Caches: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:261-267 [Conf]
  51. Preeti Ranjan Panda, Nikil D. Dutt
    Behavioral Array Mapping into Multiport Memories Targeting Low Power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:268-273 [Conf]
  52. Richard M. Chou, Kewal K. Saluja
    Sequential Circuit Testing: From DFT to SFT. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:274-278 [Conf]
  53. Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth
    Synthesis for Testability by Two-Clock Control. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:279-283 [Conf]
  54. Sudipta Bhawmik, Indradeep Ghosh
    A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:284-288 [Conf]
  55. Debashis Bhattacharya, S. Freeman, W. Lin
    Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:289-296 [Conf]
  56. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    Efficient Implementation of Multiple On-Chip Signature Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:297-302 [Conf]
  57. Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya
    New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:303-309 [Conf]
  58. Walden C. Rhines
    Developing A New Approach For Multimedia Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:310-313 [Conf]
  59. Tom Williams
    Design For Testability: Today And In The Future. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:314-317 [Conf]
  60. Kimberly D. Emerson
    Asynchronous Design - An Interesting Alternative. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:318-321 [Conf]
  61. Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho
    Delay-Insensitive Carry-Lookahead Adders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:322-328 [Conf]
  62. Radhakrishna Nagalla, Graham R. Hellestrand
    A Visual Approach for Asynchronous Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:329-335 [Conf]
  63. Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi
    An Asynchronous Morphological Processor for Multi-Media Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:336-341 [Conf]
  64. K. Nanda, S. K. Desai, S. K. Roy
    A New Methodology for the Design of Asynchronous Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:342-347 [Conf]
  65. Raj S. Mitra, Bishnupriya Bhattacharya, Luciano Lavagno
    Asynchronous Implementation of Synchronous Esterel Specifications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:348-355 [Conf]
  66. Dinesh Bhatia
    Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:356-359 [Conf]
  67. Eshwar Belani, Ravi Mittal
    A General Reconfiguration Technique for Fault Tolerant Processor Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:360-363 [Conf]
  68. Gosta Pada Biswas, Idranil Sen Sengupta
    Design of t-UED/AUED Codes from Berger's AUED Code. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:364-369 [Conf]
  69. Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar
    A Novel Reconfigurable Co-Processor Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:370-375 [Conf]
  70. Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs
    Characterization and Implicit Identification of Sequential Indistinguishability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:376-380 [Conf]
  71. Srikanth Venkataraman, W. Kent Fuchs
    Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:381-387 [Conf]
  72. Abhijit Chatterjee, Naveena Nagi
    Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:388-392 [Conf]
  73. Heebyung Yoon, Abhijit Chatterjee, Joseph L. A. Hughes
    Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:393-397 [Conf]
  74. Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi
    Pseudoduplication - An ACOB Technique for Single-Ended Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:398-402 [Conf]
  75. Premal Buch, Ernest S. Kuh
    SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:403-407 [Conf]
  76. Pramodchandran N. Variyam, Abhijit Chatterjee
    FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State Representation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:408-412 [Conf]
  77. Haiming Jin, Ravishankar K. Iyer, Mei-Chen Hsueh
    FAMAS: FAult Modeling via Adaptive Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:413-419 [Conf]
  78. D. L. Grundy, M. Bozic, John V. Hatfield
    Development of an Analogue Microprocessor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:420-424 [Conf]
  79. V. Ravindra Babu, Baquer Mazhari, M. M. Hasan
    An Expert System Approach to Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:425-428 [Conf]
  80. Pradip Mandal, V. Visvanathan
    A Self-Biased High Performance Folded Cascode CMOS Op-Amp. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:429-434 [Conf]
  81. K. Ravi Shankar, K. Radhakrishna Rao, Srinivasan Venkatraman
    Tuning Schemes for Transmission Zeros of Continuous-Time Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:435-438 [Conf]
  82. K. Ravi Shanker, Vinita Vasudevan
    Synthesis of Analog CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:439-445 [Conf]
  83. Ashley Rasquinha, N. Ranganathan
    C3L: A Chip for Connected Component Labeling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:446-450 [Conf]
  84. Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri
    Micropipeline Architecture for Multiplier-less FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:451-456 [Conf]
  85. Palash Sarkar, Bimal K. Roy, Pabitra Pal Choudhury
    VLSI Implementation of Modulo Multiplication Using Carry Free Addition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:457-460 [Conf]
  86. Tales Cleber Pimenta, Luiz Lenarth G. Vermaas, Paulo César Crepaldi, Robson L. Moreno
    The Design of A Digital IC for Thyristor Triggering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:461-464 [Conf]
  87. Rana Barua, Samik Sengupta
    Architectures for Arithmetic over GF(2m). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:465-469 [Conf]
  88. Irith Pomeranz, Sudhakar M. Reddy
    On the Detection of Reset Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:470-474 [Conf]
  89. Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
    Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:475-481 [Conf]
  90. C. P. Ravikumar, Vikas Jain, Anurag Dod
    Faster Fault Simulation Through Distributed Computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:482-487 [Conf]
  91. Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler
    Deriving Signal Constraints to Accelerate Sequential Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:488-494 [Conf]
  92. Elizabeth M. Rudnick, Janak H. Patel
    Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:495-503 [Conf]
  93. Hortensia Mecha, Milagros Fernández
    Interconnection Delay and Clock Cycle Selection in High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:504-505 [Conf]
  94. Thomas Charles Wilson, Gary William Grewal
    Shake And Bake: A Method of Mapping Code to Irregular DSPs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:506-508 [Conf]
  95. Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
    A Simulation Methodology for Software Energy Evaluation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:509-510 [Conf]
  96. Rolf Drechsler
    Pseudo Kronecker Expressions for Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:511-513 [Conf]
  97. James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal
    Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:514-515 [Conf]
  98. Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien
    A Method for Synthesizing Area Efficient Multilevel PTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:516-519 [Conf]
  99. Ron Lin
    Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:520-522 [Conf]
  100. R. Maheshwari, S. S. S. P. Rao, E. G. Poonach
    FPGA Implementation of Median Filter. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:523-524 [Conf]
  101. Subhashish Mukherjee, C. Srinivasan, Vivek Pawar, Sumeet Mathur, Kiran Godbole, Eric Soenen
    A 2.5 V 10 bit SAR ADC. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:525-526 [Conf]
  102. Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Parallel Decoder for Cellular Automata Based Byte Error Correcting Code. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:527-528 [Conf]
  103. Gosta Pada Biswas, Indranil Sengupta
    A Design Technique of TSC Checker for Borden's Code. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:529-530 [Conf]
  104. Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal
    An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:531-533 [Conf]
  105. Irith Pomeranz, Sudhakar M. Reddy
    On Full Reset as a Design-For-Testability Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:534-536 [Conf]
  106. Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy
    Impact of Partial Reset on Fault Independent Testing and BIST. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:537-539 [Conf]
  107. Raghuram S. Tupuri, Jacob A. Abraham
    A Novel Hierarchical Test Generation Method for Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:540-541 [Conf]
  108. Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel
    Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:542-544 [Conf]
  109. Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana
    Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I/sub DDQ/ Testing in BiCMOS and CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:545-546 [Conf]
  110. Chunduri Rama Mohan, S. Mitra, Partha Pal Chaudhuri
    On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:547-563 [Conf]
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