Conferences in DBLP
Robert W. Brodersen Invited Address: The InfoPad Project: Review and Lessons Learned. [Citation Graph (0, 0)][DBLP ] Conf ] Teresa H. Y. Meng Invited Address: A Wireless Portable Video-On-Demand System. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , Sunil D. Sherlekar , G. Venkatesh Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha , Sujit Dey A Power Management Methodology for High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Suhrid A. Wadekar , Alice C. Parker , C. P. Ravikumar Freedom: Statistical Behavioral Estimation of System Energy and Power. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , Sunil D. Sherlekar , G. Venkatesh Extensions to Programmable DSP architectures for Reduced Power Dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Naveed A. Sherwani , Prashant Sawkar Embedded Tutorial: Layout Driven Synthesis or Synthesis Driven Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Z. V. Apanovich , Alexander G. Marchuk Top-Down Approach to Technology Migration for Full-Custom Mask Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Bharat Krishna , C. Y. Roger Chen , Naresh Sehgal Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Subhashis Majumder , Subhas C. Nandy , Bhargab B. Bhattacharya Partitioning VLSI Floorplans by Staircase Channels for Global Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Das , Susmita Sur-Kolay , Bhargab B. Bhattacharya Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Weste , David J. Skellern , Terry Percival Invited Paper: Broadband U-NII Wireless Data. [Citation Graph (0, 0)][DBLP ] Conf ] Bengt Svantesson , Shashi Kumar , Ahmed Hemani A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL. [Citation Graph (0, 0)][DBLP ] Conf ] Anupam Basu , Raj S. Mitra , Peter Marwedel Interface Synthesis for Embedded Applications in a Co Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Pradeep K. Mishra , Somnath Paul , S. Venkataraman , Rajat Gupta Hardware/Software Co-design of a High-end Mixed Signal Microcontroller. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep K. Lodha , Shashank Gupta , M. Balakrishnan , Subhashis Banerjee Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Sinha , Mahesh Mehendale mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , Somdipta Basu Roy , Sunil D. Sherlekar , G. Venkatesh Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Anteneh Alemu Abbo An Embedded Processor for Integrated Navigation Receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Ansgar Drolshagen , Walter Anheier , C. Chandra Sekhar A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. [Citation Graph (0, 0)][DBLP ] Conf ] S. Balakrishnan , Soumitra Kumar Nandy Arbitrary Precision Arithmetic - SIMD Style. [Citation Graph (0, 0)][DBLP ] Conf ] C. G. Hiremath , Sriram Jayasimha Improving Concurrency for Cosine-modulated Filterbank Windowing. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasan Venkatraman , Srikanth Natarajan , K. Radhakrishna Rao A Low Power Video Frequency Continuous Time Filter. [Citation Graph (0, 0)][DBLP ] Conf ] C. Srinivasan A Technique to Improve Capture Range of a PLL in PRML Read Channel. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivasan Venkatraman , Srikanth Natarajan , K. Radhakrishna Rao A New Tuning Scheme for Continuous Time Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Cauwenberghs Design and VLSI Implementation of an Adaptive Delta-Sigma Modulator. [Citation Graph (0, 0)][DBLP ] Conf ] S. Pradeep Kiran , K. Radhakrishna Rao A Novel Translinear Principle Based BiMOS Transconductor. [Citation Graph (0, 0)][DBLP ] Conf ] C. F. Prince , Vinita Vasudevan Symbolic Analysis of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Hsiao , Gurjeet S. Saund , Elizabeth M. Rudnick , Janak H. Patel Partial Scan Selection Based on Dynamic Reachability and Observability Information. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Balakrishnan , Srimat T. Chakradhar Peripheral Partitioning and Tree Decomposition for Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Sumit Gupta , Akshay Jajoo Synthesis of Testable RTL Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Srivaths Ravi , Indradeep Ghosh , Rabindra K. Roy , Sujit Dey Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Huy Nguyen , Rabindra K. Roy , Abhijit Chatterjee Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Debesh K. Das , Indrajit Chaudhuri , Bhargab B. Bhattacharya Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Roy , Prithviraj Banerjee , Majid Sarrafzadeh Partitioning sequential circuits for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Pramit Chavda , James Jacob , Vishwani D. Agrawal Optimizing Logic Design Using Boolean Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Pranav Ashar Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Das , Samrat Sen , Mohan Rangan , Rupesh Nayak , G. N. Nandakumar False Path Detection at Transistor Level. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Krishna , Ramamurti Chandramouli , N. Ranganathan Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Raghu Burra , Dinesh Bhatia Timing Driven Multi-FPGA Board Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Adriano M. Pereira , Tales César Pimenta , Robson L. Moreno , Edgar Charry R. , Alberto M. Jorge Design of a Measurement and Interface Integrated Circuit for Characterization of Switched Current Memory Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Saeid Nooshabadi , G. S. Visweswaran , D. Nagchoudhuri Current Mode Ternary D/A Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Prakash Gopalakrishnan , Vinita Vasudevan A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nagu R. Dhanwada , Ranga Vemuri Constraint Allocation in Analog System Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory E. Beers , Lizy Kurian John Novel Memory Bus Driver/Receiver Architecture for Higher Throughput. [Citation Graph (0, 0)][DBLP ] Conf ] Cyrus Bamji , Ravi Varadarajan Incremental Autojogging using Range Spaces. [Citation Graph (0, 0)][DBLP ] Conf ] V. Rajesh , Ajai Jain Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Sitaram Yadavalli , Sanjay Sengupta Impact and Cost of Modeling Memories for ATPG for Partial Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Test Compaction Objectives for Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ananta K. Majhi , Vishwani D. Agrawal Mixed-Signal Test. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip Bhavsar A Method for Synchronizing IEEE 1149.1 Test Access Port for Chip Level Testability Access. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed Fadle Abdulla , C. P. Ravikumar , Anshul Kumar Hybrid Testing Schemes Based on Mutual and Signature Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Pallab K. Chatterjee Keynote Address: The Networked Society - Enabled by DSP Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey Invited Address: Hybrid Reconfigurable Processors - The Road to Low-Power Consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Sodini , Jeffrey C. Gealow , Zubair A. Talib , Ichiro Masaki Invited Address: Integrated Memory/Logic Architecture for Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] S. Srivastava , S. C. Bose , B. P. Mathur , Arti Noor , Raj Singh , A. S. Mandal , K. Prabhakaran , A. Karmakar , Chandra Shekhar , Sudhir Kumar , Amit K. Agarwal Evolution of Architectural Concepts and Design Methods of Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Ascia , Vincenzo Catania A Framework for a Parallel Architecture Dedicated to Soft Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard Laurent , G. Bosco , Gabriele Saucier Fast Arithmetic on Xilinx 5200 FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] S. K. Misra , R. K. Kolagotla , Hosahalli R. Srinivas , J. C. Mo , M. S. Diamondstein VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay. [Citation Graph (0, 0)][DBLP ] Conf ] R. V. K. Pillai , Asim J. Al-Khalili , Dhamin Al-Khalili A Low Power Floating Point Accumulator. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Jain , Charles Chien , Etan G. Cohen , Leader Ho Simulation and Synthesis of VLSI Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Partha S. Roop , Arcot Sowmya CFSMcharts: A New Language for Microprocessor Based system Design. [Citation Graph (0, 0)][DBLP ] Conf ] Bharat P. Dave , Niraj K. Jha COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Johnny Öberg , Axel Jantsch , Anshul Kumar An Object-Oriented Concept for Intelligent Library Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-Hyun Heo , Alice C. Parker , C. P. Ravikumar An Evolutionary Approach to System Redesign. [Citation Graph (0, 0)][DBLP ] Conf ] Ananta K. Majhi , Vishwani D. Agrawal Tutorial: Delay Fault Models and Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Amey Karkare , Manoj Singla , Ajai Jain Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit. [Citation Graph (0, 0)][DBLP ] Conf ] S. Balajee , Ananta K. Majhi Automated AC (Timing) Characterization for Digital Circuit Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Vinay Dabholkar , Sreejit Chakravarty Computing Stress Tests for Gate Oxide Shorts. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Ben Jone , Sunil R. Das A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Selvaraj , Miroslawa Nowicka , Tadeusz Luba Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] M. Bhaskar Sherigar , A. S. Mahadevan , K. Senthil Kumar , Sumam David A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Sitanshu Jain , M. Balakrishnan , Anshul Kumar , Shashi Kumar Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. [Citation Graph (0, 0)][DBLP ] Conf ] P. S. Nagendra Rao , C. S. Jayathirtha , C. S. Raghavendra Prasad New Net Models for Spectral Netlist Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Atul Wokhlu , R. Venkat Krishna , Sandeep Agarwal A Low Voltage Mixed Signal ASIC for Digital Clinical Thermometer. [Citation Graph (0, 0)][DBLP ] Conf ] Nagarajan Ranganathan , Rajat Anand , Girish Chiruvolu A VLSI ATM Switch Architecture for VBR Traffic. [Citation Graph (0, 0)][DBLP ] Conf ] Pradeep Prabhakaran , Prithviraj Banerjee Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Vinoo Srinivasan , Ranga Vemuri A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Zhang Yang , Rajesh K. Gupta A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis Tasks. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Saha , Anantha Chandrakasan Web-based Distributed VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Xijiang Lin , Irith Pomeranz , Sudhakar M. Reddy MIX: A Test Generation System for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Kewal K. Saluja On Test Pattern Compaction Using Random Pattern Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Subhashis Majumder , Michael L. Bushnell , Vishwani D. Agrawal Path Delay Testing: Variable-Clock Versus Rated-Clock. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Venkataraman , W. Kent Fuchs , Janak H. Patel Diagnostic Simulation of Sequential Circuits Using Fault Sampling. [Citation Graph (0, 0)][DBLP ] Conf ] C. S. Raghu , S. Sundaram Distributed Logic Simulation Algorithm using Preemption of Inconsistent Events. [Citation Graph (0, 0)][DBLP ] Conf ] Tony Tsang A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh S. Parthasarathy , Ramalingam Sridhar Double Pass Transistor Logic for High Performance Wave Pipeline Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Pinaki Mazumder , Shriram Kulkarni , Mayukh Bhattacharya , Alejandro F. González Circuit Design using Resonant Tunneling Diodes. [Citation Graph (0, 0)][DBLP ] Conf ] Rung-Bin Lin , Meng-Chiou Wu A New Statistical Approach to Timing Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay A. Nebhrajani , Nayan Suthar Finite State Machines: A Deeper Look into Synthesis Optimization for VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Chattopadhyay , Parimal Pal Chaudhuri Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] P. Srinivasa Rao , James Jacob A Fast Two-level Logic Minimizer. [Citation Graph (0, 0)][DBLP ] Conf ] Cyrus Bamji , Manjit Borah An Improved Cost Heuristic for Transistor Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Gitanjali Swamy , Stephen A. Edwards , Robert K. Brayton Efficient Verification and Synthesis using Design Commonalities. [Citation Graph (0, 0)][DBLP ] Conf ] Sreeranga P. Rajan , Masahiro Fujita Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammed Fadle Abdulla , C. P. Ravikumar , Anshul Kumar On-Chip Signature Checking for Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Chattopadhyay , Parimal Pal Chaudhuri Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence. [Citation Graph (0, 0)][DBLP ] Conf ] Hugo De Man Invited Address: Future Systems-on-a-Chip: Impact on Engineering Education. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Jain Panel: Challenges for Future Systems on a Chip. [Citation Graph (0, 0)][DBLP ] Conf ] 