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Conferences in DBLP

VLSI Design (vlsid)
1993 (conf/vlsid/1993)

  1. Osamu Karatsu
    On the History and Future Detecion of VLSI Design and CAD - Japanese Perspective. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:3-4 [Conf]
  2. Vinaya Kumar Singh, A. A. Diwan
    A Heuristic for Decomposition in Multi-Level Logic Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:5-8 [Conf]
  3. Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose
    Combining State Assignment with PLA Folding. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:9-14 [Conf]
  4. Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
    State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:15-20 [Conf]
  5. Alexandre Yakovlev
    Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:21-24 [Conf]
  6. Mario Kovac, N. Ranganathan, M. Varanasi
    SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:25-30 [Conf]
  7. Chowdhury S. Rahman, Mi Lu
    A Partition Approach to Find the Length of the Longest Common Subsequence. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:31-36 [Conf]
  8. R. Bouraoui, Alain Guyot, G. Walker
    Design of an On-Line Euclidean Processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:37-40 [Conf]
  9. Raghu Sastry, N. Ranganathan, Horst Bunke
    Hardware Algorithms for Polygon Matching. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:41-44 [Conf]
  10. Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni
    Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:45-50 [Conf]
  11. Yves Bertrand, Frédéric Bancel, Michel Renovell
    A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:51-54 [Conf]
  12. Amitava Majumdar, Sarma Sastry
    Statistical Analysis of Controllability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:55-60 [Conf]
  13. Wen-Ben Jone, Sunil R. Das
    CACOP - A Random Pattern Testability Analyzer. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:61-64 [Conf]
  14. B. Krieger
    PLATO: A Tool for Computation of Exact Signal Probabilities. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:65-68 [Conf]
  15. Irith Pomeranz, Sudhakar M. Reddy
    On the Generation of Weights for Weighted Pseudo Random Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:69-72 [Conf]
  16. Suhail Ahmed, T. V. Nagesh, Ramoji Rao, B. Naveen, P. K. Fangaria, K. S. Raghunathan
    FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:73-79 [Conf]
  17. Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta
    NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:80-83 [Conf]
  18. Ed P. Huijbregts, Jochen A. G. Jess
    A Multiple Terminal Net Routing Algorithm Using Failure Prediction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:84-89 [Conf]
  19. Joon Shik Lim, S. Sitharama Iyengar, Si-Qing Zheng
    Euclidean Shortest Path Problem with Rectilinear Obstacles. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:90-93 [Conf]
  20. Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
    On Optimum Cell Models for Over-the-Cell Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:94-99 [Conf]
  21. Mahesh Mehendale, Kaushik Roy
    Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:100-103 [Conf]
  22. P. R. Suresh Kumar, Mandyam-Komar Srinivas, James Jacob
    Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:104- [Conf]
  23. S. Raman, M. M. Hasan
    A PLA-Based FSM Design Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:105-106 [Conf]
  24. Dipanwita Roy Chowdhury, Supratik Chakraborty, Parimal Pal Chaudhuri
    Synthesis of Self-Checking Sequential Machines Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:107- [Conf]
  25. Himanshu S. Mazumdar
    A Multilayered Feed Forward Neural Network Suitable for VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:108- [Conf]
  26. Sandip Das, Bhargab B. Bhattacharya
    Via Minimization in Channel Routing by Layout Modification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:109-110 [Conf]
  27. C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer
    High Level Design Experiences with IDEAS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:110- [Conf]
  28. P. Marimuthu, K. S. Raghunathan
    BEST: Bond Editor and Test Vector Translator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:111- [Conf]
  29. Biswadip Mitra, Parimal Pal Chaudhuri
    A Scheme for Synthesizing Testable VLSI Designs with Minimum Area Overhead. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:112- [Conf]
  30. Jason Cong, Moazzem Hossain, Naveed A. Sherwani
    A Provably Good Algorithm for k-Layer Topological Planar Routing Problems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:113- [Conf]
  31. Kanti Prasad, Aditya Goel
    Preparing Engineers to Meet the Challenges of the 21st Century Through VLSI Education. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:114-117 [Conf]
  32. W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana
    Use of Storage Elements as Primitives for Modelling Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:118-123 [Conf]
  33. D. Crestani, A. Aguila, L. Eudeline, M.-H. Gentil, C. Durante
    A Hierarchical Test Generation Using High Level Primitives. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:124-127 [Conf]
  34. Bernd Becker, Rolf Krieger
    FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:128-131 [Conf]
  35. M. Srinivas, Lalit M. Patnaik
    A Simulation-Based Test Generation Scheme Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:132-135 [Conf]
  36. Rochit Rajsuman, D. A. Penry
    Coverage of Bridging Faults by Random Testing in IDDQ Test Environment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:136-139 [Conf]
  37. Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin
    Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:140-143 [Conf]
  38. Choong Gun Oh, Hee Yong Youn, Vijay K. Raj
    Algorithm-Based Concurrent Error Detection for FFT Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:144-147 [Conf]
  39. Lih-Gwo Jeng, Liang-Gee Chen
    Rate-Optimal DSP Synthesis by Pipeline and Minimum Undolding. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:148-153 [Conf]
  40. Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
    Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:154-159 [Conf]
  41. Luigi Dadda
    A Simplified High Speed Parallel Input Convolver. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:160-165 [Conf]
  42. V. Visvanathan, Nibedita Mohanty, S. Ramanathan
    An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:166-171 [Conf]
  43. Arjun Rajagopal, Belli Kuttanna, Balaji Janakiraman, Rajarshi Mukherjee, Joy Shetler
    A Reconfigurable Arithmetic Processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:172-175 [Conf]
  44. S. Ramanathan, Nibedita Mohanty, V. Visvanathan
    A Methodology for Generating Application Specific Tree Multipliers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:176-179 [Conf]
  45. Hyuk-Jae Jang, Barry M. Pangrle
    GB: A New Grid-Based Binding Approach for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:180-185 [Conf]
  46. Ahmed Hemani
    Self-Organization and its Application to Binding. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:186-191 [Conf]
  47. Thomas Charles Wilson, Nilanjan Mukherjee, M. K. Garg, Dilip K. Banerji
    An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:192-197 [Conf]
  48. Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau
    Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:198-201 [Conf]
  49. Byung Wook Jeon, Chidchanok Lursinsap
    MS3: Micro-Rollback and Self-Recovery System Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:202-207 [Conf]
  50. Khushro Shahookar, W. Khamisani, Pinaki Mazumder, Sudhakar M. Reddy
    Genetic Beam Search for Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:208-213 [Conf]
  51. Akhilesh Tyagi
    A Module Generator Development Environment: Area Estimation and Design-Space Exploration Encapsulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:214-217 [Conf]
  52. G. Pannerselvam, A. Sarkar, Subir Bandyopadhyay, Graham A. Jullien
    Area Efficient VLSI Design with Cells of Controllable Complexity. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:218-221 [Conf]
  53. Rajeev Govindan, Michael A. Langston, Siddharthan Ramachandramurthi
    A Practical Approach to Layout Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:222-225 [Conf]
  54. Bjarne Hald, Jan Madsen
    Performance Aspects of Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:226-229 [Conf]
  55. Aditya Agrawal, P. V. Srinivas, G. Sreenivas, Uttiya Dasgupta
    LATCHECK: A Latchup Checker for VLSI Layouts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:230-235 [Conf]
  56. S. Bapat, James P. Cohoon
    A Parallel VLSI Circuit Layout Methodology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:236-241 [Conf]
  57. Krishnaiyan Thulasiraman, Prasad R. Chalasani, Parimala Thulasiraman, M. A. Comeau
    Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and a Unified Approach to VLSI Layout Compaction and Wire Balancing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:242-245 [Conf]
  58. Kumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal
    Architecture of a Min-Max Simulator on MARS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:246-249 [Conf]
  59. Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
    A Massively Parallel, Micro-Grained VLSI Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:250-255 [Conf]
  60. Pradip Bose, John-David Wellman
    MIPS-Driven Early Design and Analysis of VLSI CPU Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:256-259 [Conf]
  61. Anna Antola, Alberto Avai, Luca Breveglieri, Andrea Paparella
    Modular Design Methodologies for Image Processing Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:260-263 [Conf]
  62. Sunil D. Sherlekar
    Export of VLSI Design and CAD: Present and Future. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:264- [Conf]
  63. Ankan K. Pramanick, Sudhakar M. Reddy
    On Unified Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:265-268 [Conf]
  64. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
    A Path Delay Fault Simulator for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:269-274 [Conf]
  65. Sandeep Bhatia, Niraj K. Jha
    Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:275-280 [Conf]
  66. S. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy
    Delay Fault Test Generation with Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:281-286 [Conf]
  67. K. S. V. Gopalarao, Uttiya Dasgupta, Rajeev Jain, Duane S. Boning, Purnendu K. Mozumder, V. Chandramouli
    An Integrated Technology CAD System for Process and Device Designers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:287-292 [Conf]
  68. Peter Kist, N. Simon, Mattie Sim, E. Marks, Kees Schot, A. Sarotama
    A Mechanism for Fine-Grain Concurrent Sharing of Design Data Among CAD Tools. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:293-298 [Conf]
  69. M. V. Rao, M. Balakrishnan, Anshul Kumar
    DESSERT: Design Space Exploration of RT Level Components. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:299-304 [Conf]
  70. Klaus D. Müller-Glaser, J. Bortolazzi, Y. Tanurhan, J. Ernst
    CAE in Requirements Definition and Specification for Complex Microelectronic Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:305-310 [Conf]
  71. Sankaran Karthik, Jacob A. Abraham, Raymond P. Voith
    Optimizations for Behavioral/RTL Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:311-316 [Conf]
  72. Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga
    A Shared Memory Parallel Algorithm for Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:317-322 [Conf]
  73. Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Minimization of Logic Functions Using Essential Signature Sets. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:323-328 [Conf]
  74. Olivier Coudert, Jean Christophe Madre
    Towards a Symbolic Logic Minimization Algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:329-334 [Conf]
  75. Susanta Misra, Biswadip Mitra, Parimal Pal Chaudhuri
    A Novel Scheme for Synthesis of Easily Testable Finite State Machines Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:335-340 [Conf]
  76. Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
    NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:341-346 [Conf]
  77. Dinesh Somasekhar, V. Visvanathan
    A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:347-350 [Conf]
  78. Joydeep Ghosh, Nari Krishnamurthy
    Fault-Tolerant Arbitration in Multichip Crossbar Switches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:351-356 [Conf]
  79. João C. Vital, José E. Franca
    High-Speed A/D-D/A Conversion System with Flexible Testing Capabilities. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:357-362 [Conf]
  80. M. Shamanna, Sterling R. Whitaker
    A Carry Select Adder with Conflict Free Bypass Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:363-366 [Conf]
  81. Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    New CMOS Structures for the Synthesis of Dominant Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:367-370 [Conf]
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