Conferences in DBLP
Robert A. Pease Invited Talk: The Information Appliance and Its Interface to the Analog World: Easy - Or Not So Easy. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod K. Agarwal Invited Talk: Embedded Test for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Ramayya Kumar Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go? [Citation Graph (0, 0)][DBLP ] Conf ] Nagaraj Ns , Poras T. Balsara , Cyrus Cantrell Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Li-Fu Chang , Abhay Dubey , Keh-Jeng Chang , Robert Mathews , Ken Wong Incorporating Process Induced Effects into RC Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Marko P. Chew , Sharad Saxena , Thomas F. Cobourn , Purnendu K. Mozumder , Andrzej J. Strojwas A New Methodology for Concurrent Technology Development and Cell Library Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Bedabrata Pain , Guang Yang , Brita Olson , Timothy Shaw , Monico Ortiz , Julie Heynssens , Chris Wrigley , Charlie Ho A Low-Power Digital Camera-on-a-Chip Implemented in CMOS Active Pixel Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Anantha Chandrakasan , Abram P. Dancy , James Goodman , Thomas Simon A Low-Power Wireless Camera System. [Citation Graph (0, 0)][DBLP ] Conf ] Paulo F. Flores , José C. Costa , Horácio C. Neto , José C. Monteiro , João P. Marques Silva Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , Sunil D. Sherlekar Low Power Code Generation of Multiplication-free Linear Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Nithya Raghavan , Venkatesh Akella , Smita Bakshi Automatic Insertion of Gated Clocks at Register Transfer Level. [Citation Graph (0, 0)][DBLP ] Conf ] Kavita Nair , Ramesh Harjani Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid. [Citation Graph (0, 0)][DBLP ] Conf ] P. K. Singh , Sriram Jayasimha A Low-Complexity, Reduced-Power Viterbi Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Basabi Bhaumik , Pravas Pradhan , G. S. Visweswaran , Rajamohan Varambally , Anand Hardi A Low Power 256 KB SRAM Design. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Kewal K. Saluja , Kozo Kinoshita Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] R. D. (Shawn) Blanton IDDQ-Testability of Tree Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] M. Jamoussi Test-Vector Prediction of M-Testable Iterative Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit T. Zachariah , Sreejit Chakravarty A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Basabi Bhaumik , G. S. Visweswaran , R. Lakshminarasimhan A New Test Compression Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Gabriel Robins , Anish Singh , Alexander Zelikovsky New and Exact Filling Algorithms for Layout Density Control. [Citation Graph (0, 0)][DBLP ] Conf ] Franklin M. Schellenberg Design for Manufacturing in the Semiconductor Industry: The Litho/Design Workshops. [Citation Graph (0, 0)][DBLP ] Conf ] Akis Doganis , James C. Chen Interconnect Simple, Accurate and Statistical Models Using On-Chip Measurements for Calibration. [Citation Graph (0, 0)][DBLP ] Conf ] Rashmi Goswami , V. Srinivasan , M. Balakrishnan MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] V. Rajesh , Rajat Moona Processor Modeling for Hardware Software Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Mattias O'Nils , Axel Jantsch Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos A. Kountouris , Christophe Wolinski Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Ludovic Jacomme , Frédéric Pétrot , Rajesh K. Bawa Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Manpreet S. Khaira nvited Talk: Micro-2010: Lead Microprocessor for 2010 - Myth or Reality? [Citation Graph (0, 0)][DBLP ] Conf ] Satrajit Gupta , Lalit M. Patnaik Exact Output Response Computation of RC Interconnects under Polynomial Input Waveforms. [Citation Graph (0, 0)][DBLP ] Conf ] A. B. Bhattacharyya , Saudas Dey Sub-Circuit Analysis for Power Supply Rejection Ratio in Regulated Cascode Operational Transconductance Amplifiers and Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Shabbir H. Batterywala , H. Narayanan Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Savithri Sundareswaran , David Blaauw , Abhijit Dharchoudhury A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Thacker , Wendy Belluomini , Chris J. Myers Timed Circuit Synthesis Using Implicit Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip Mandal , V. Visvanathan A New Approach for CMOS Op-Amp Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert K. Brayton , Sunil P. Khatri Multi-Valued Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil P. Khatri , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Sequential Multi-Valued Network Simplification using Redundancy Removal. [Citation Graph (0, 0)][DBLP ] Conf ] Shugang Wei , Kensuke Shimizu Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Macchiarulo , Pierluigi Civera Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. [Citation Graph (0, 0)][DBLP ] Conf ] Partha Pratim Chakrabarti , Pallab Dasgupta , Partha Pratim Das , Arnob Roy , Shuvendu K. Lahiri , Mrinal Bose Controlling State Explosion in Static Simulation by Selective Composition. [Citation Graph (0, 0)][DBLP ] Conf ] Rathish Jayabharathi , Manuel A. d'Abreu , Jacob A. Abraham FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Maurer Efficient Simulation for Hierarchical and Partitioned Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ajoy C. Siddabathuni , M. Balakrishnan Simulation and Modeling of a Multicast ATM Switch. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip A. Thaker , Mona E. Zaghloul , Minesh B. Amin Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Zbigniew Kalbarczyk , Janak H. Patel , Myeong S. Lee , Ravishankar K. Iyer An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Debaleena Das , Nur A. Touba A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard Courtois , Jean-Michel Karam , Salvador Mir , Marcelo Lubaszewski , Vladimir Székely , Márta Rencz , Klaus Hofmann , Manfred Glesner Design and Test of MEMs. [Citation Graph (0, 0)][DBLP ] Conf ] Vishnu A. Patankar , Alok Jain , Randal E. Bryant Formal Verification of an ARM Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Srivatsan Srinivasan , Parminder Singh Chhabra , Praveen Kumar Jaini , Adnan Aziz , Lizy Kurian John Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Jatindra Kumar Deka , Pallab Dasgupta , P. P. Chakrabarti An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Noppanunt Utamaphethai , R. D. (Shawn) Blanton , John Paul Shen Superscalar Processor Validation at the Microarchitecture Level. [Citation Graph (0, 0)][DBLP ] Conf ] Tamarah Arons , Amir Pnueli Verifying Tomasulo's Algoithm by Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy Casas , Hannah Honghua Yang , Manpreet Khaira , Mandar Joshi , Thomas Tetzlaff , Steve W. Otto , Erik Seligman Logic Verification of Very Large Circuits Using Shark. [Citation Graph (0, 0)][DBLP ] Conf ] Ingo Sander , Axel Jantsch Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons. [Citation Graph (0, 0)][DBLP ] Conf ] Pankaj Chauhan , Pallab Dasgupta , P. P. Chakrabarti Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Anupam Basu , Rainer Leupers , Peter Marwedel Array Index Allocation under Register Constraints in DSP Programs. [Citation Graph (0, 0)][DBLP ] Conf ] D. V. R. Murthy , S. Ramachandran , S. Srinivasan Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. [Citation Graph (0, 0)][DBLP ] Conf ] M. N. Mahesh , Satrajit Gupta , Mahesh Mehendale Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Avinash K. Gautam , Jagdish C. Rao , Rohit Rathi , H. Udayakumar A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] S. Ramanathan , V. Visvanathan , S. K. Nandy Synthesis of Configurable Architectures for DSP Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhakar Bobba , Ibrahim N. Hajj , Naresh R. Shanbhag Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Peichen Pan , Guohua Chen Optimal Retiming for Initial State Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Tai-Hung Liu , Malay K. Ganai , Adnan Aziz , Jeffrey L. Burns Performance Driven Synthesis for Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP ] Conf ] B. N. V. Malleswara Gupta , H. Narayanan , Madhav P. Desai A State Assignment Scheme Targeting Performance and Area. [Citation Graph (0, 0)][DBLP ] Conf ] S. Ramesh Efficient Translation of Statecharts to Hardware Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chitrasena Bhat , Niranjan N. Chiplunkar Heuristic Technology Mapper For Lut Based Fpgas. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Jawahar Jain , Masahiro Fujita Efficient Scheduling Techniques for ROBDD Construction. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Saxena , Peichen Pan , C. L. Liu The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Narayon Recent Advances in BDD Based Representations for Boolean Functions: A Survey. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Zhang , Kaushik Roy , Sudipta Bhawmik POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Pradeep Prabhakaran , Prithviraj Banerjee , Jim E. Crenshaw , Majid Sarrafzadeh Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Mircea R. Stan Optimal Voltages and Sizing for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Michael L. Bushnell , Ganapathy Parthasarathy , Rajesh Ramadoss Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Krishna , N. Ranganathan , Narayanan Vijaykrishnan Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Bulent Basaran , Kiran Ganesh , Raymond Y. K. Lau , Artour Levin , Miles McCoo , Srinivasan Rangarajan , Naresh Sehgal GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Avaneendra Gupta , John P. Hayes Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP ] Conf ] C. S. Raghu , Suravi Bhowmik , Poorvaja Ramani , S. Sundaram COST Circuit Optimization SysTem in ASIC Library Development Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sudhakar Muddu , Egino Sarto Interconnect Optimization Strategies for High-Performance VLSI Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Vittal , Lauren Hui Chen , Malgorzata Marek-Sadowska , Kai-Ping Wang , Sherry Yang Modeling Crosstalk in Resistive VLSI Interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Noel Menezes , Chung-Ping Chen Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Keerthi Heragu , Janak H. Patel , Vishwani D. Agrawal A Test Generator for Segment Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Subhashis Majumder , Bhargab B. Bhattacharya , Vishwani D. Agrawal , Michael L. Bushnell A Complete Characterization of Path Delay Faults through Stuck-at Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Jue Wu , Elizabeth M. Rudnick A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Shashank K. Mehta , Sharad C. Seth Empirical Computation of Reject Ratio in VLSI Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Susanta Chakraborty , Sandip Das , Debesh K. Das , Bhargab B. Bhattacharya Synthesis of Symmetric Functions for Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Sudip Chakrabarti , Abhijit Chatterjee Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv V. Joshi , Wei Hwang Design Considerations and Implementation of a High Performance Dynamic Register File. [Citation Graph (0, 0)][DBLP ] Conf ] Kolin Paul , P. Dutta , Dipanwita Roy Chowdhury , Prasanta Kumar Nandi , Parimal Pal Chaudhuri A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Augustine , William E. Lynch , Yuke Wang , Asim J. Al-Khalili Lossy Compression of Images Using Logic Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Bhunia , Soumya K. Ghosh , Pramod Kumar , Partha Pratim Das , Jayanta Mukherjee Design, Simulation and Synthesis of an ASIC for Fractal Image Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Lov K. Grover Invited Talk: Quantum Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Sree Ganesan , Ranga Vemuri FAAR: A Router for Field-Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Das , Subhas C. Nandy , Bhargab B. Bhattacharya High Performance MCM Routing: A New Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Jayadeva Sequential Chaotic Annealing and its Application to Multilayer Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Gi-Joon Nam , Karem A. Sakallah , Rob A. Rutenbar Satisfiability-Based Detailed FPGA Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Sudhakar Muddu Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Joonbae Park , Yido Koo , Wonchan Kim A Semi-Digital Delay Locked Loop for Clock Skew Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Nagu R. Dhanwada , Adrián Núñez-Aldana , Ranga Vemuri Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Pramodchandran N. Variyam , Junwei Hou , Abhijit Chatterjee Test Generation for Analog Circuits Using Partial Numerical Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Fang-Cheng Chang , Melissa Kwok , Kenneth Rachlin , Robert Pack Silicon-Level Physical Verification of Sub Wavelength(tm) Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Sharad Malik , José C. Monteiro , Luciano Lavagno CAD Techniques for Embedded System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel d'Arbreu , Abhijit Chatterjee Manufacturability of Mixed Signal Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sudip Nag , H. K. Verma , Kaushik Roy VLSI Signal Processing in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Razdan , Apurva Kalia , Manu Lauria Verification of Systems-on-Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Jerzy Tyszer , Sanjay Patel Built-In Self-Test for Systems on Silicon. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Anand Raghunathan , Sujit Dey Low Power Design Methodologies for Systems-on-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Bupesh Pandita , Subir K. Roy Design and Implementation of Viterbi Decoder Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip K. Kar , Subir K. Roy TECHMIG: A Layout Tool for Technology Migration. [Citation Graph (0, 0)][DBLP ] Conf ] Onuttom Narayan , Jaijeet S. Roychowdhury Analyzing Forced Oscillators with Multiple Time Scales. [Citation Graph (0, 0)][DBLP ] Conf ] Unni Narayanan , Georgios I. Stamoulis , Rabindra K. Roy Characterizing Individual Gate Power Sensitivity in Low Power Design. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Manish Sharma , R. K. Patney Improving the Diagnosability of Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Ajay Mittal Hierarchical Delay Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] 