Conferences in DBLP
Mahesh Mehendale , Sunil D. Sherlekar Power Reduction Techniques for Portable DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Parimal Pal Chaudhuri , Dipanwita Roy Chowdhury , Kolin Paul , Biplab K. Sikdar Theory and Applications of Cellular Automata for VLSI Design and Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Rubin A. Parekhji Test Techniques and Trade-offs for Embedded Cores and Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Laurence Nagel , Jaijeet S. Roychowdhury Computer-aided Design of RF Communication Systems: Techniques and Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Harjani Analog Circuits for Wireless Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer , Sandeep K. Gupta New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Frank P. Higgins , Sudipta Bhawmik Core Based ASIC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Yoji Kajitani , Atsushi Takahashi , Kengo R. Azegami , Shigetoshi Nakatake Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Khurram Muhammad Low Power VLSI Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Avtar Saini Computing and Communication in the New Millennium. [Citation Graph (0, 0)][DBLP ] Conf ] Ajoy K. Bose EDA-The Next Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano , Warren Savage , John Chilton IP Reuse in System on a Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Liqiong Wei , Kaushik Roy , Vivek De Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. [Citation Graph (0, 0)][DBLP ] Conf ] M. N. Mahesh , Mahesh Mehendale Low Power Realization of Residue Number System Based FIR Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Savithri Sundareswaran , R. Venkatesan , S. Bhaskar An Assertion Based Technique for Transistor Level Dynamic Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Russell Henning , Chaitali Chakrabarti Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv V. Joshi , Wei Hwang , S. C. Wilson , Ghavam V. Shahidi , Ching-Te Chuang A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Sinha , Anantha Chandrakasan Energy Aware Software. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip Bose , Jacob A. Abraham Performance and Functional Verification of Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Partha S. Roop , Arcot Sowmya , S. Ramesh Automatic Component Matching Using Forced Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Dipankar Sarkar Status Condition Analysis during Data Path Verification of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Basant Rajan , R. K. Shyamasundar Modeling VHDL in Multiclock ESTEREL. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Ghosh , Ranga Vemuri Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind Rajawat , M. Balakrishnan , Anshul Kumar nterface Synthesis: Issues and Approaches. [Citation Graph (0, 0)][DBLP ] Conf ] T. Vinod Kumar Gupta , Purvesh Sharma , M. Balakrishnan , Sharad Malik Processor Evaluation in an Embedded Systems Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Schaffer , Renate Merker , Francky Catthoor Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. [Citation Graph (0, 0)][DBLP ] Conf ] Aviral Shrivastava , Mohit Kumar , Sanjiv Kapoor , Shashi Kumar , M. Balakrishnan Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Dick , Niraj K. Jha COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Werner Metz , Tinku Acharya Challenges of Merging Digital Imaging and Wireless Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Arun K. Majumdar , Nirav Patel Design of an ASIC for Straight Line Detection in an Image. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Sarkar Digital Imaging with Wireless Data Services. [Citation Graph (0, 0)][DBLP ] Conf ] Kolin Paul , Ranadeep Ghosal , Biplab K. Sikdar , Santashil Pal Chaudhuri , Dipanwita Roy Chowdhury GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images. [Citation Graph (0, 0)][DBLP ] Conf ] Kolin Paul , Parimal Pal Chaudhuri , Dipanwita Roy Chowdhury Scalable Pipelined Micro-Architecture for Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Akis Doganis Interconnect Statistical Modeling: Structures and Measurement Methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] Rajat Chaudhry , Rajendran Panda , Tim Edwards , David Blaauw Design and Analysis of Power Distribution Networks with Accurate RLC Models. [Citation Graph (0, 0)][DBLP ] Conf ] Jinseong Choi , Sungjun Chun , Nanju Na , Madhavan Swaminathan , Larry Smith A Methodology for the Placement and Optimization of Decoupling Capacitors for Gigahertz Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mondira Deb Pant , Pankaj Pant , D. Scott Wills , Vivek Tiwari Inductive Noise Reduction at the Architectural Level. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyou Zhao , Kaushik Roy Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel A. d'Abreu Manufacturing and Test Considerations in System-On-Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jitendra Khare , Hans T. Heineken , M. d'Abreu Cost Trade-Offs in System On Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Saghir A. Shaikh , Jitendra Khare , Hans T. Heineken Manufacturability and Testability Oriented Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Charles H. Ouyang , Hans T. Heineken , Jitendra Khare , Saghir A. Shaikh , M. d'Abreu Maximizing Wafer Productivity Through Layout Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Raghuram S. Tupuri , Jacob A. Abraham , Daniel G. Saab Hierarchical Test Generation for Systems On a Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Chittaranjan A. Mandal , R. M. Zimmer A Genetic Algorithm for the Synthesis of Structured Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram Govindarajan , Vinoo Srinivasan , Preetham Lakshmikanthan , Ranga Vemuri A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Raghunathan , Srivaths Ravi , Ganesh Lakshminarayana High-Level Synthesis with Variable-Latency Components. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi K. Srikantam , N. Ranganathan , Srikanth Srinivasan CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Abdel Ejnioui , N. Ranganathan Design Partitioning on Single-Chip Emulation Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Abdel Ejnioui , N. Ranganathan Routing on Switch Matrix Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ranjit K. Dash , T. Pramod , Vinita Vasudevan , M. Ramakrishna A Transistor Level Placement Tool for Custom Cell Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Das On the Transistor Sizing Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Sushil Chandra Jain , Shashi Kumar , Anshul Kumar Evaluation of Various Routing Architectures for Multi-FPGA Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Liang Wu , Wangning Long , Hongbing Fan A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Bhunia , Subhashis Majumder , Ayan Sircar , Susmita Sur-Kolay , Bhargab B. Bhattacharya Topological Routing Amidst Polygonal Obstacles. [Citation Graph (0, 0)][DBLP ] Conf ] Helvio P. Peixoto , Margarida F. Jacome , Ander Royo A Tight Area Upper Bound for Slicing Floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Hideo Fujiwara A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Hideyuki Ichihara , Kozo Kinoshita , Irith Pomeranz , Sudhakar M. Reddy Test Transformation to Improve Compaction by Statistical Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroki Wada , Toshimitsu Masuzawa , Kewal K. Saluja , Hideo Fujiwara Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal Choice of Tests for Logic Verification and Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Sumners , Jayanta Bhadra , Jacob A. Abraham Automatic Validation Test Generation Using Extracted Control Models. [Citation Graph (0, 0)][DBLP ] Conf ] John Scarisbric DSP-The Real Time Technology for the New Millennium. [Citation Graph (0, 0)][DBLP ] Conf ] Grant Martin Surviving the SOC Revolution: The Platform Approach to SOC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sabyasachi Dey , Bhargab B. Bhattacharya , Malay Kumar Kundu , Tinku Acharya A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh T. N. Rajaram , Vinita Vasudevan Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD. [Citation Graph (0, 0)][DBLP ] Conf ] Bedabrata Pain , Guang Yang , Monico Ortiz , Kenneth McCarty , Julie Heynssens , Bruce Hancock , Thomas Cunningham , Chris Wrigley , Charlie Ho A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Dutta , Deepak Singh , Essam Abu-Ghoush , Vijay Mehra Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Fu-Chiung Cheng , Chuin-Ren Wang Specification and Design of a Quasi-Delay-Insensitive Java Card. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Das Trends in Communication Technology and its Impact on Semiconductor. [Citation Graph (0, 0)][DBLP ] Conf ] Sachin S. Sapatnekar Capturing the Effect of Crosstalk on Delay. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Frank Cano , Duane Young , Deepak Vohra , Manoj Das A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jeegar Tilak Shah , Madhav P. Desai , Sugata Sanyal Inductance Characterization of Small Interconnects Using Test-Signal Method. [Citation Graph (0, 0)][DBLP ] Conf ] Bhargab B. Bhattacharya , Alexej Dmitriev , Michael Gössel Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Surendra Bommu , Srimat T. Chakradhar , Kiran B. Doreswamy Resource-Constrained Compaction of Sequential Circuit Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Gh. Mohammad , Kewal K. Saluja , Alex Yap Testing Flash Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Mayer , Albrecht P. Stroele A Versatile BIST Technique Combining Test Registers and Accumulators. [Citation Graph (0, 0)][DBLP ] Conf ] Subir K. Roy , Hiroaki Iwashita , Tsuneo Nakata Dataflow Analysis for Resource Contention and Register Leakage Properties. [Citation Graph (0, 0)][DBLP ] Conf ] Subhash Chandra , Rajat Moona Retargetable Functional Simulator Using High Level Processor Models. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Maurer , William J. Schilp State-Machine Based Logic Simulation Using Three Logic Values. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Boppana , Indradeep Ghosh , Rajarshi Mukherjee , Jawahar Jain , Masahiro Fujita Hierarchical Error Diagnosis Targeting RTL Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Aarti Gupta , Pranav Ashar Fast Error Diagnosis for Combinational Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Xia , Pranav Ashar Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Anil Sharma , C. P. Ravikumar Efficient Implementation of ADPCM Codec. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Gaurav Chandra , Ashutosh Verma Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Karthikeyan Madathil , Jagdish C. Rao , Subash G. Chandar , Amitabh Menon , Avinash K. Gautam , Amit M. Brahme , H. Udayakumar A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Ruchir Puri , Ching-Te Chuang SOI Digital Circuits: Design Issues. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjeev Kumar Maheshwari , R. S. Krishanan , G. S. Visweswaran Jitter Estimation Methodology for Clock Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjeev Kumar Maheshwari , G. S. Visweswaran A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] B. Senapati , C. K. Maiti , Nirmal B. Chakrabarti Silicon Heterostructure Devices for RF Wireless Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Baidya Nath Ray , Parimal Pal Chaudhuri , Prasanta Kumar Nandi Design of OTA Based Field Programmable Analog Array. [Citation Graph (0, 0)][DBLP ] Conf ] Mayukh Bhattacharya , Pinaki Mazumder Convergence Issues in Resonant Tunneling Diode Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan J. Falkowski , Sudha Kannurao Spectral Theory of Disjunctive Decomposition for Balanced Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] B. Suresh , Biswadeep Chaterjee , R. Harinath Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene Goldberg , Alexander Saldanha Timing Analysis with Implicitly Specified False Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Kamal S. Khouri , Niraj K. Jha Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. [Citation Graph (0, 0)][DBLP ] Conf ] Kanishka Lahiri , Sujit Dey , Anand Raghunathan Performance Analysis of Systems with Multi-Channel Communication Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Prabir Dasgupta , Santanu Chattopadhyay , Indranil Sengupta An ASIC for Cellular Automata Based Message Authentication. [Citation Graph (0, 0)][DBLP ] Conf ] Prabir Dasgupta , Santanu Chattopadhyay , Indranil Sengupta Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sasikumar Cherubal , Abhijit Chatterjee An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Biplab K. Sikdar , Kolin Paul , Gosta Pada Biswas , Parimal Pal Chaudhuri , Vamsi Boppana , Cliff Yang , Sobhan Mukherjee Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Kolin Paul , Dipanwita Roy Chowdhury Application of GF(2p) CA in Burst Error Correcting Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Gloria Huertas , Diego Vázquez , Adoración Rueda , José L. Huertas Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell. [Citation Graph (0, 0)][DBLP ] Conf ] Jeongjin Roh , Jacob A. Abraham A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters. [Citation Graph (0, 0)][DBLP ] Conf ] Juha Plosila , Tiberiu Seceleanu Design of Synchronous Action Systems. [Citation Graph (0, 0)][DBLP ] Conf ] 