Conferences in DBLP

VLSI Design (vlsid)
2001 (conf/vlsid/2001)

1. Noel Menezes, Sachin S. Sapatnekar
   Optimization and Analysis Techniques for the Deep Submicron Regime. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:3-4 [Conf]
   
2. Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda
   Embedded Memories in System Design: Technology, Application, Design and Tools. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:5-6 [Conf]
   
3. Sudipta Bhawmik
   ntroduction to SystemC. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:7-8 [Conf]
   
4. Anand Raghunathan, Sujit Dey
   Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:9-10 [Conf]
   
5. Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty
   IBM's Blue Logic Design Methodology-Circuits and Physical Design. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:11-12 [Conf]
   
6. Deepak Kataria
   Next Generation Network Processors. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:13-15 [Conf]
   
7. Mahesh Mehendale, Santhosh Kumar Amanna
   Functional Verification of Programmable DSP Cores. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:16-17 [Conf]
   
8. V. Ranganatha, R. Sunda
   System Level Testability Issues of Core Based System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:18- [Conf]
   
9. Ramesh Harjani, Jackson Harvey
   Tutorial: CMOS Analog Circuits for Wireless Communications. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:18- [Conf]
   
10. Anupam Rastogi, M. Balakrishnan, Anshul Kumar
    Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:23-28 [Conf]
    
11. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:29-35 [Conf]
    
12. Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair
    Performance Considerations in Embedded DSP based System-On-a-Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:36-41 [Conf]
    
13. Abhijit K. Deb, Ahmed Hemani, Johnny Öberg, Adam Postula, Dan Lindqvist
    Hardware Software Codesign of DSP System Using Grammar Based Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:42-47 [Conf]
    
14. Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari
    A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:48-0 [Conf]
    
15. Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan
    Battery Life Estimation of Mobile Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:57-63 [Conf]
    
16. Pavan Kumar, Mani B. Srivastava
    Power-aware Multimedia Systems using Run-time Prediction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:64-69 [Conf]
    
17. Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau
    Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:70-75 [Conf]
    
18. Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
    ASIP Design Methodologies : Survey and Issues. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:76-0 [Conf]
    
19. G. Surendra, S. K. Nandy, Paul Sathya
    ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:85-90 [Conf]
    
20. Vineet Sahula, C. P. Ravikumar
    The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:91-96 [Conf]
    
21. Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt
    Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:97-102 [Conf]
    
22. Anand L. D'Souza, Michael S. Hsiao
    Error Diagnosis of Sequential Circuits Using Region-Based Mode. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:103-0 [Conf]
    
23. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    On Improving Static Test Compaction for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:111-116 [Conf]
    
24. Sitaram Yadavalli, Sandip Kundu
    On Fault-Simulation Through Embedded Memories On Large Industrial Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:117-121 [Conf]
    
25. Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay
    A Novel Strategy to Test Core Based Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:122-127 [Conf]
    
26. Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara
    Testable Design of Sequential Circuits with Improved Fault Efficiency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:128-133 [Conf]
    
27. Sameer Sharma, Michael S. Hsiao
    Combination of Structural and State Analysis for Partial Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:134-0 [Conf]
    
28. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:143-148 [Conf]
    
29. Srivaths Ravi, Niraj K. Jha
    Synthesis of System-on-a-chip for Testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:149-156 [Conf]
    
30. Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri
    Timing Verification and Delay Test Generation for Hierarchical Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:157-162 [Conf]
    
31. Jian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel
    A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:163-0 [Conf]
    
32. Wolfgang Günther, Rolf Drechsler
    Implementation of Read- k-times BDDs on Top of Standard BDD Packages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:173-178 [Conf]
    
33. Siddharth R. Phanse, R. K. Shyamasundar
    Application of Esterel for Modelling and Verification of Cachet Protocol on CRF Memory Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:179-188 [Conf]
    
34. Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr
    Design Verification and Functional Testing of FiniteState Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:189-195 [Conf]
    
35. Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
    Design Of Provably Correct Storage Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:196-0 [Conf]
    
36. Rex Min, Manish Bhardwaj, Seong-Hwan Cho, Eugene Shih, Amit Sinha, Alice Wang, Anantha Chandrakasan
    Low-Power Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:205-210 [Conf]
    
37. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
    Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:211-214 [Conf]
    
38. Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
    Average Power in Digital CMOS Circuits using Least Square Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:215-220 [Conf]
    
39. Amit Sinha, Anantha Chandrakasan
    Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:221-226 [Conf]
    
40. Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal
    Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:227-0 [Conf]
    
41. Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar
    Accurate Power Macro-modeling Techniques for Complex RTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:235-241 [Conf]
    
42. Abhijit M. Lele, S. K. Nandy
    Architecture of Reconfigurable a Low Power Gigabit AT Switch. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:242-247 [Conf]
    
43. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir
    Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:248-253 [Conf]
    
44. Vishal Dalal, C. P. Ravikumar
    Software Power Optimizations In An Embedded System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:254-0 [Conf]
    
45. Sree Ganesan, Ranga Vemuri
    Library Binding for High-Level Synthesis of Analog Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:261-268 [Conf]
    
46. Jackson Harvey, Ramesh Harjani
    An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:269-273 [Conf]
    
47. Sanjay Mohan, Michael L. Bushnell
    A Code Transition Delay Model for ADC Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:274-282 [Conf]
    
48. Alper Demir, David E. Long, Jaijeet S. Roychowdhury
    Computing Phase Noise Eigenfunctions Directly from Harmonic Balance/Shooting Matrices. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:283-0 [Conf]
    
49. K. Yan
    Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:291-298 [Conf]
    
50. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee, Nagaraj Shenoy
    Fpga Hardware Synthesis From Matlab. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:299-304 [Conf]
    
51. U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary, Mahmut T. Kandemir
    Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:305-310 [Conf]
    
52. Wolfgang Günther, Rolf Drechsler
    Performance Driven Optimization for MUX based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:311-316 [Conf]
    
53. Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri
    Application Specific Macro Based Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:317-0 [Conf]
    
54. Qinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya
    Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:327-332 [Conf]
    
55. Sujit T. Zachariah, Sreejit Chakravarty
    A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:333-338 [Conf]
    
56. Mark A. Hillebrand, Thomas Schurger, Peter-Michael Seidel
    How to Half Wire Lengths in the Layout of Cyclic Shifter. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:339-344 [Conf]
    
57. Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta
    Partitioning Routing Area into Zones with Distinct Pins. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:345-0 [Conf]
    
58. Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami
    Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:353-358 [Conf]
    
59. Qinwei Xu, Pinaki Mazumder, Zheng-Fan Li
    Transmission Line Modeling by Modified Method of Characteristics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:359-364 [Conf]
    
60. Nagaraj Ns, Poras T. Balsara, Cyrus Cantrell
    Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:365-370 [Conf]
    
61. Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante
    Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:371-0 [Conf]
    
62. Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
    An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:379-384 [Conf]
    
63. Dilip K. Bhavsar, Rishan Tan
    Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:385-390 [Conf]
    
64. Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi
    Efficient Signature-Based Fault Diagnosis Using Variable Size Windows. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:391-396 [Conf]
    
65. Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
    A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:397-402 [Conf]
    
66. Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly
    Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:403-0 [Conf]
    
67. Vikas Agrawal, Anand Pande, Mahesh Mehendale
    High Level Synthesis Of Multi-Precision Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:411-416 [Conf]
    
68. L. Wang, A. E. A. Almaini
    Multilevel Logic Minimization Using Functional Don't Cares. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:417-424 [Conf]
    
69. Supratik Chakraborty, Rajeev Murgai
    Complexity Of Minimum-Delay Gate Resizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:425-430 [Conf]
    
70. Krishnendu Chakrabarty, Andrew Exnicios, Rajatish Mukherjee
    Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:431-0 [Conf]
    
71. Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura
    Scaling Up Of Wave Pipelines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:439-445 [Conf]
    
72. Alexander Worm, Holger Lamm, Norbert Wehn
    Vlsi Architectures For High-Speed Map Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:446-453 [Conf]
    
73. Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly
    Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:454-459 [Conf]
    
74. Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busa
    Synthesizing A Long Latency Unit Within Vliw Processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:460-0 [Conf]
    
75. Omkaram Nalamasu, Pat G. Watson, Raymond A. Cirelli, Jeff Bude, Isik C. Kizilyalli, Ross A. Kohler
    Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:469-469 [Conf]
    
76. Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax
    Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:470-474 [Conf]
    
77. G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele
    erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:475-478 [Conf]
    
78. Nihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao
    Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:479-0 [Conf]
    
79. R. K. Jarwal, Durga Misra
    Degradation Of Nmosfets During High-Field Injection With Reverse Biased Voltage At Source And Drain Junctions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:485-490 [Conf]
    
80. B. Prasad, P. J. George, Chandra Shekhar
    High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:491-494 [Conf]
    
81. Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai
    An On-Chip Coupling Capacitance Measurement Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:495-499 [Conf]
    
82. Shabbir H. Batterywala, H. Narayanan
    Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:500-0 [Conf]
    
83. Dinesh Pamunuwa, Hannu Tenhunen
    Repeater Insertion To Minimise Delay In Coupled Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:513-517 [Conf]
    
84. N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das
    Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:518-523 [Conf]
    
85. Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Switching Noise Analysis Framework For High Speed Logic Families. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:524-530 [Conf]
    
86. V. Sankara Subramanian, C. P. Ravikumar
    Estimating Crosstalk From Vlsi Layouts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:531-0 [Conf]