Conferences in DBLP

VLSI Design (vlsid)
2002 (conf/vlsid/2002)

1. Biswadip Mitra
   Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:3-4 [Conf]
   
2. Kazuo Yano
   LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration Era. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:5- [Conf]
   
3. Aart J. de Geus
   Electronic Industry on Fire: How to Survive and Thrive. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:6- [Conf]
   
4. Martin F. H. Schuurmans
   Digital Watermarking. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:7-0 [Conf]
   
5. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
   Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:11-13 [Conf]
   
6. Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven
   System-Level Design of Embedded Media Systems (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:14-15 [Conf]
   
7. Stefan Rusu, Manoj Sachdev, Christer Svensson, B. Nauta
   Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:16-17 [Conf]
   
8. M. V. Atre, P. S. Subramanian, H. Narayanan
   Mathematical Methods in VLSI (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:18-19 [Conf]
   
9. Vishwani D. Agrawal, Michael L. Bushnell
   Electronic Testing for SOC Designers (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:20- [Conf]
   
10. Luciano Lavagno, Sujit Dey, Rajesh K. Gupta
    Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:21-23 [Conf]
    
11. R. Lal, P. R. Apte, K. N. Bhat, G. Bose, S. Chandra, D. K. Sharma
    MEMS: Technology, Design, CAD and Applications (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:24-25 [Conf]
    
12. Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
    Logic Design of Asynchronous Circuits (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:26-0 [Conf]
    
13. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
    Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:31-38 [Conf]
    
14. Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha
    Topological Analysis for Leakage Prediction of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:39-44 [Conf]
    
15. Rahul Kumar, C. P. Ravikumar
    Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:45-50 [Conf]
    
16. Fei Li, Lei He, Kewal K. Saluja
    Estimation of Maximum Power-Up Current. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:51-0 [Conf]
    
17. Joong-Ho Kim, Erdem Matoglu, Jinwoo Choi, Madhavan Swaminathan
    Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:59-64 [Conf]
    
18. Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
    Dynamic Noise Analysis with Capacitive and Inductive Coupling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:65-70 [Conf]
    
19. Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata
    Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:71-76 [Conf]
    
20. Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
    Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:77-0 [Conf]
    
21. Rupesh S. Shelar, Sachin S. Sapatnekar
    An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:87-92 [Conf]
    
22. Hiroshi Saito, Alex Kondratyev, Takashi Nanya
    Design of Asynchronous Controllers with Delay Insensitive Interface. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:93-98 [Conf]
    
23. Debasis Samanta, Nishant Sinha, Ajit Pal
    Synthesis of High Performance Low Power Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:99-104 [Conf]
    
24. Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
    Improvement of ASIC Design Processes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:105-0 [Conf]
    
25. Haris Lekatsas, Jörg Henkel
    ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:113-120 [Conf]
    
26. Rung-Bin Lin, Chi-Ming Tsai
    Weight-Based Bus-Invert Coding for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:121-125 [Conf]
    
27. Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram
    Software-Only Bus Encoding Techniques for an Embedded System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:126-131 [Conf]
    
28. Payam Heydari, Massoud Pedram
    Interconnect Energy Dissipation in High-Speed ULSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:132-0 [Conf]
    
29. N. S. Nagaraj, Poras T. Balsara, Cyrus Cantrell
    Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:141- [Conf]
    
30. P. K. Datta, S. Sanyal, D. Bhattacharya
    Losses in Multilevel Crossover in VLSI Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:142-146 [Conf]
    
31. Qinwei Xu, Pinaki Mazumder
    Rational ABCD Modeling of High-Speed Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:147-0 [Conf]
    
32. Kuo-Hsing Cheng, Shun-Wen Cheng
    Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:155-159 [Conf]
    
33. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    A New Synthesis of Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:160-165 [Conf]
    
34. Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
    Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:166-171 [Conf]
    
35. D. Sarkar
    Register Transfer Operation Analysis during Data Path Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:172-0 [Conf]
    
36. Ashok K. Murugavel, N. Ranganathan
    A Real Delay Switching Activity Simulator Based on Petri Net Modeling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:181-186 [Conf]
    
37. Sanjukta Bhanja, N. Ranganathan
    Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:187-192 [Conf]
    
38. Debasis Samanta, Ajit Pal
    Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:193-198 [Conf]
    
39. Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
    Minimizing Energy Consumption for High-Performance Processing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:199-0 [Conf]
    
40. A. B. Bhattacharyya, Shrutin Ulman
    PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:207-212 [Conf]
    
41. Peter M. Lee, Shinji Ito, Takeaki Hashimoto, Junji Sato, Tomomasa Touma, Goichi Yokomizo
    A Parallel and Accelerated Circuit Simulator with Precise Accuracy. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:213-218 [Conf]
    
42. Srinath R. Naidu
    Timing Yield Calculation Using an Impulse-Train Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:219-224 [Conf]
    
43. H. C. Srinivasaiah, Navakanta Bhat
    Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:225-0 [Conf]
    
44. Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar
    Exploring the Number of Register Windows in ASIP Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:233-238 [Conf]
    
45. Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
    Architecture Implementation Using the Machine Description Language LISA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:239-244 [Conf]
    
46. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Framework for Design Space Exploration of Parameterized VLSI Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:245-250 [Conf]
    
47. S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri
    An Evolutionary Scheme for Cosynthesis of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:251-0 [Conf]
    
48. Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi
    Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:261-267 [Conf]
    
49. Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
    A Power Minimization Technique for Arithmetic Circuits by Cell Selection. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:268-273 [Conf]
    
50. Yunsi Fei, Niraj K. Jha
    Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:274-281 [Conf]
    
51. Tohru Ishihara, Kunihiro Asada
    An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:282-287 [Conf]
    
52. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu
    Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:288-0 [Conf]
    
53. S. Natarajan, A. Marshall
    Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:297-298 [Conf]
    
54. Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh
    Transistor Flaring in Deep Submicron-Design Considerations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:299-304 [Conf]
    
55. Shuzhou Fang, Zeyi Wang, Xianlong Hong
    A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:305-310 [Conf]
    
56. Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh
    Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:311-316 [Conf]
    
57. Maryam Shojaei Baghini, Madhav P. Desai
    Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:317-0 [Conf]
    
58. P. Klapproth
    Embedded Tutorial: General Architectural Concepts for IP Core Re-Use. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:325-0 [Conf]
    
59. Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri
    Framework for Synthesis of Virtual Pipelines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:326-331 [Conf]
    
60. Junyu Peng, Samar Abdi, Daniel Gajski
    Automatic Model Refinement for Fast Architecture Exploration. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:332-337 [Conf]
    
61. Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck
    Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:338-344 [Conf]
    
62. Li Shang, Niraj K. Jha
    Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:345-0 [Conf]
    
63. Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida
    A Design of Analog C-Matrix Circuits Used for Signal/Data Processing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:355-359 [Conf]
    
64. Debapriya Sahu
    A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:360-365 [Conf]
    
65. Biranchinath Sahu, Aloke K. Dutta
    Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:366-371 [Conf]
    
66. Jens Lienig, Goeran Jerke, Thorsten Adler
    Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:372-0 [Conf]
    
67. Wei Chen, Massoud Pedram, Premal Buch
    Buffered Routing Tree Construction under Buffer Placement Blockages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:381-386 [Conf]
    
68. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:387-392 [Conf]
    
69. Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin
    An Adaptive Interconnect-Length Driven Placer. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:393-398 [Conf]
    
70. Stelian Alupoaei, Srinivas Katkoori
    Net Clustering Based Macrocell Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:399-0 [Conf]
    
71. Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac
    High-Level Synthesis with SIMD Units. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:407-413 [Conf]
    
72. J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir
    A Heuristic for Clock Selection in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:414-419 [Conf]
    
73. Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
    Design for Verification at the Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:420-425 [Conf]
    
74. Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya
    Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:426-0 [Conf]
    
75. Kavish Seth, S. Srinivasan
    VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:435-440 [Conf]
    
76. Hak-soo Yu, Jacob A. Abraham
    An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:441-446 [Conf]
    
77. Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout
    Architecture and Design of a High Performance SRAM for SOC Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:447-451 [Conf]
    
78. Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    VLSI Architecture for a Flexible Motion Estimation with Parameters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:452-457 [Conf]
    
79. Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau
    Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:458-0 [Conf]
    
80. Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
    Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:467-472 [Conf]
    
81. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:473-478 [Conf]
    
82. Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita
    Simultaneous Circuit Transformation and Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:479-483 [Conf]
    
83. Chunhong Chen
    Probabilistic Analysis of Rectilinear Steiner Trees. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:484-488 [Conf]
    
84. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:489-0 [Conf]
    
85. Hailong Cui, Sharad C. Seth, Shashank K. Mehta
    A Novel Method to Improve the Test Efficiency of VLSI Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:499-504 [Conf]
    
86. Sandeep Koranne
    On Test Scheduling for Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:505-510 [Conf]
    
87. Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy
    Constraint Driven Pin Mapping for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:511-516 [Conf]
    
88. Katarzyna Radecka, Zeljko Zilic
    Identifying Redundant Wire Replacements for Synthesis and Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:517-523 [Conf]
    
89. Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi
    Property-Specific Testbench Generation for Guided Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:524-0 [Conf]
    
90. Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
    A New Divide and Conquer Method for Achieving High Speed Division in Hardware. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:535-540 [Conf]
    
91. Tony Han, Sri Parameswaran
    SWASAD: An ASIC Design for High Speed DNA Sequence Matching. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:541-546 [Conf]
    
92. Martin Palkovic, Miguel Miranda, Kristof Denolf, Peter Vos, Francky Catthoor
    Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:547-552 [Conf]
    
93. Debashis Panigrahi, Clark N. Taylor, Sujit Dey
    A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:553-0 [Conf]
    
94. Qinwei Xu, Pinaki Mazumder
    Efficient Macromodeling for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:561-566 [Conf]
    
95. Silke Salewski, Erich Barke
    An Upper Bound for 3D Slicing Floorplans. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:567-572 [Conf]
    
96. Jingcao Hu, Yangdong Deng, Radu Marculescu
    System-Level Point-to-Point Communication Synthesis using Floorplanning Information. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:573-579 [Conf]
    
97. Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky
    Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:580-0 [Conf]
    
98. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Multiple Faults: Modeling, Simulation and Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:592-597 [Conf]
    
99. Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik
    Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:598-603 [Conf]
    
100. Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski
     Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:604-0 [Conf]
     
101. Sornavalli Ramanathan, Rituparna Mandal
     Low Power Solution for Wireless Applications. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:615-618 [Conf]
     
102. J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir
     Address Code and Arithmetic Optimizations for Embedded Systems. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:619-624 [Conf]
     
103. Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo
     Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:625-630 [Conf]
     
104. N. E. Crosbie, Mahmut T. Kandemir, Ibrahim Kolcu, J. Ramanujam, Alok N. Choudhary
     Strategies for Improving Data Locality in Embedded Applications. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:631-0 [Conf]
     
105. Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
     On Routing Demand and Congestion Estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:639-646 [Conf]
     
106. Supratik Chakraborty, Rajeev Murgai
     Layout-Driven Timing Optimization by Generalized De Morgan Transform. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:647-654 [Conf]
     
107. Rituparna Mandal, Dibyendu Goswami, Arup Dash
     Reducing Library Development Cycle Time through an Optimum Layout Create Flow. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:655-660 [Conf]
     
108. Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho
     A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:661-0 [Conf]
     
109. Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das
     Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:671-676 [Conf]
     
110. Irith Pomeranz, Sudhakar M. Reddy
     A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:677-682 [Conf]
     
111. Makoto Sugihara, Hiroto Yasuura
     Optimization of Test Accesses with a Combined BIST and External Test Scheme. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:683-688 [Conf]
     
112. Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
     Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:689-0 [Conf]
     
113. Dexin Li, Pai H. Chou, Nader Bagherzadeh
     Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:697-704 [Conf]
     
114. Anupam Datta, Sidharth Choudhury, Anupam Basu
     Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:705-710 [Conf]
     
115. Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha
     Input Space Adaptive Embedded Software Synthesis. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:711-718 [Conf]
     
116. Jiong Luo, Niraj K. Jha
     Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:719-0 [Conf]
     
117. Malay K. Ganai, Adnan Aziz
     Improved SAT-Based Bounded Reachability Analysis. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:729-734 [Conf]
     
118. Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti
     Open Computation Tree Logic for Formal Verification of Modules. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:735-740 [Conf]
     
119. Raik Brinkmann, Rolf Drechsler
     RTL-Datapath Verification using Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:741-746 [Conf]
     
120. Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima
     Verification of an Industrial CC-NUMA Server. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:747-0 [Conf]
     
121. Sagar S. Sabade, D. M. H. Walker
     Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:755-760 [Conf]
     
122. C. P. Ravikumar, Rahul Kumar
     Divide-and-Conquer IDDQ Testing for Core-Based System Chips. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:761-766 [Conf]
     
123. Yun Shao, Irith Pomeranz, Sudhakar M. Reddy
     Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:767-772 [Conf]
     
124. Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi
     Test Solution for OTA Based Analog Circuits. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:773-0 [Conf]
     
125. Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji
     Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:781-788 [Conf]
     
126. Sanjeev Patel
     Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:789-794 [Conf]
     
127. Ranjit Yashwante, Bhalchandra Jahagirdar
     IEEE 1394a_2000 Physical Layer ASIC. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:795-800 [Conf]
     
128. T. Datta, C. S. Muralidharan
     Definition, Design & Development of the IXE2424 Network Switch/Router ASIC. [Citation Graph (0, 0)][DBLP]
     VLSI Design, 2002, pp:801-802 [Conf]