Conferences in DBLP

VLSI Design (vlsid)
2003 (conf/vlsid/2003)

1. Gene A. Frantz
   Personal and Portable: The Evolving Definition. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:3- [Conf]
   
2. Ted Vucurevich
   Living at the Edge. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:4- [Conf]
   
3. Rajeev Madhavan
   India-Building the Tall, Thin VLSI Engineer. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:5- [Conf]
   
4. A. Vasudevan
   Advances in VLSI Design and Product Development Challenges. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:6- [Conf]
   
5. Sandeep K. Shukla, Jean-Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta
   High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:9-14 [Conf]
   
6. Rajiv V. Joshi, Kaushik Roy
   Design of Deep Sub-Micron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:15-16 [Conf]
   
7. Rubin A. Parekhji
   Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:17- [Conf]
   
8. Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran
   Specification and Design of Multi-Million Gate SOCs. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:18-19 [Conf]
   
9. Natarajan Mahadeva Iyer, M. K. Radhakrishnan
   ESD Reliability Challenges for RF/Mixed Signal Design & Processing. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:20-21 [Conf]
   
10. Krithi Ramamritham, Kavi Arya
    System Support for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:22-0 [Conf]
    
11. Anantha Nag, K. Radhakrishna Rao
    Narrow Band Noise Suppression Scheme for improving Signal to Noise Ratio. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:25-29 [Conf]
    
12. Sounil Biswas, Baquer Mazhari
    A Path Sensitization Technique for Testing of Switched Capacitor Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:30-35 [Conf]
    
13. Prashant Admane, Manoj Patasani, Biju Viswanathan
    A Novel RF Front-End Chipset For ISM Band Wireless Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:36-41 [Conf]
    
14. Saikat Sarkar, Padmanava Sen, Arvind Raghava, Sudipto Chakarborty, Joy Laskar
    Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25µm CMOS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:42-0 [Conf]
    
15. Muthukumar Venkatesan, Henry Selvaraj
    Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:51-57 [Conf]
    
16. Cristinel Ababei, Kia Bazargan
    Timing Minimization by Statistical Timing hMetis-based Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:58-63 [Conf]
    
17. Sachin B. Patkar, H. Narayanan
    An Efficient Practical Heuristic For Good Ratio-Cut Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:64-69 [Conf]
    
18. Jong-Sheng Cherng, Sao-Jie Chen
    An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:70-0 [Conf]
    
19. Rohit Pandey, Santanu Chattopadhyay
    Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach". [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:79-84 [Conf]
    
20. Zhibin Dai, Dilip K. Banerji
    Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:85-90 [Conf]
    
21. Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri
    A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:91-0 [Conf]
    
22. Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao
    Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:99-104 [Conf]
    
23. R. Srinivasan, Navakanta Bhat
    Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:105-109 [Conf]
    
24. Najeebuddin Hakim, V. Ramgopal Rao, J. Vasi
    Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:110-115 [Conf]
    
25. Manisha Pattanaik, Swapna Banerjee
    A New Approach to Analyze a Sub-micron CMOS Inverter. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:116-121 [Conf]
    
26. V. Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau
    Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:122-127 [Conf]
    
27. D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao
    Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:128-0 [Conf]
    
28. Arun Krishnamachary, Jacob A. Abraham
    Effects of Multi-cycle Sensitization on Delay Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:137-142 [Conf]
    
29. Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja
    Exclusive Test and its Applications to Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:143-148 [Conf]
    
30. Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
    A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:149-154 [Conf]
    
31. Samir Roy, U. Maulik, Biplab K. Sikdar
    Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:155-160 [Conf]
    
32. Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Design Of A Universal BIST (UBIST) Structure. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:161-166 [Conf]
    
33. Petros Drineas, Yiorgos Makris
    SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:167-0 [Conf]
    
34. Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar
    Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:177-182 [Conf]
    
35. Vadali Srinivasa Murty, P. C. Reghu Raj, S. Raman
    Design of a high speed string matching co-processor for NLP. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:183-188 [Conf]
    
36. Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli
    A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:189-194 [Conf]
    
37. Kyriakos Vlachos, Nikos A. Nikolaou, Theofanis Orphanoudakis, Stylianos Perissakis, Dionisios N. Pnevmatikatos, George Kornaros, J. A. Sanchez, George E. Konstantoulakis
    Processing and Scheduling Components in an Innovative Network Processor Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:195-201 [Conf]
    
38. Srikar Movva, S. Srinivasan
    A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:202-207 [Conf]
    
39. Bipul Das, Swapna Banerjee
    A Memory Efficient 3-D DWT Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:208-0 [Conf]
    
40. Mohammad Gh. Mohammad, Kewal K. Saluja
    Electrical Model For Program Disturb Faults in Non-Volatile Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:217-222 [Conf]
    
41. S. Mahapatra, S. Shukuri, Jeff Bude
    Substrate Bias Effect on Cycling Induced Performance Degradation of Flash EEPROMs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:223-226 [Conf]
    
42. Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin
    Analyzing Soft Errors in Leakage Optimized SRAM Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:227-233 [Conf]
    
43. Li Ding 0002, Pinaki Mazumder
    The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:234-0 [Conf]
    
44. Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula
    Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:243-248 [Conf]
    
45. Pao-Ann Hsiung, Shu-Yu Cheng
    Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:249-254 [Conf]
    
46. Souvik Basu, Rajat Moona
    High Level Synthesis from Sim-nML Processor Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:255-260 [Conf]
    
47. Yong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang
    Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:261-0 [Conf]
    
48. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Embedding Security in Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:269-270 [Conf]
    
49. Subhayan Sen, Sk. Iqbal Hossain, Kabirul Islam, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Cryptosystem Designed for Embedded System Security. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:271-276 [Conf]
    
50. Chandrama Shaw, Debashis Chatterji, Pradipta Maji, Subhayan Sen, B. N. Roy, Parimal Pal Chaudhuri
    A Pipeline Architecture for Encompression (Encryption + Compression) Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:277-282 [Conf]
    
51. Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan
    VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:283-0 [Conf]
    
52. Koushik K. Das, Richard B. Brown
    Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:291-296 [Conf]
    
53. Chandramouli Gopalakrishnan, Srinivas Katkoori
    Resource Allocation and Binding Approach for Low Leakage Power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:297-302 [Conf]
    
54. Debasis Samanta, Ajit Pal
    Synthesis of Dual-VT Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:303-308 [Conf]
    
55. J. Veerendra Kumar, K. Radhakrishna Rao
    A Low-Voltage Low Power CMOS Companding Filter. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:309-314 [Conf]
    
56. W. Kuang, J. S. Yuan
    An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:315-319 [Conf]
    
57. Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri
    A Methodology for Accurate Modeling of Energy Dissipation in Array Structures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:320-0 [Conf]
    
58. Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa
    Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:329-334 [Conf]
    
59. Irith Pomeranz, Sudhakar M. Reddy
    Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:335-340 [Conf]
    
60. Santanu Chattopadhyay, K. Sudarsana Reddy
    Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:341-346 [Conf]
    
61. C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra
    Mutual Testing based on Wavelet Transforms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:347-352 [Conf]
    
62. Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
    New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:353-360 [Conf]
    
63. Sagar S. Sabade, D. M. H. Walker
    Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:361-0 [Conf]
    
64. Jiong Luo, Niraj K. Jha
    Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:369-375 [Conf]
    
65. Thomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer
    Mapping and Scheduling for Architecture Exploration of Networking SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:376-381 [Conf]
    
66. Praveen Bhojwani, Rabi N. Mahapatra
    Interfacing Cores with On-chip Packet-Switched Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:382-387 [Conf]
    
67. Robert H. Bell Jr., Lizy Kurian John
    Interface Design Techniques for Single-Chip Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:388-394 [Conf]
    
68. Bedabrata Pain, Bruce Hancock, Thomas Cunningham, Guang Yang, Suresh Seshadri, Julie Heynssens, Chris Wrigley
    CMOS Digital Imager Design from a System-on-a-chip Perspective. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:395-400 [Conf]
    
69. Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar
    Extending Platform-Based Design to Network on Chip Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:401-0 [Conf]
    
70. Shabbir H. Batterywala, Narendra V. Shenoy
    A Method to Estimate Slew and Delay in Coupled Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:411-416 [Conf]
    
71. Vani Prasad, Madhav P. Desai
    Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:417-422 [Conf]
    
72. Pan Zhongliang
    Bridging Fault Detections for Testable Realizations of Logic Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:423-0 [Conf]
    
73. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Efficient RTL Power Estimation for Large Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:431-439 [Conf]
    
74. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
    Transition Activity Estimation for General Correlated Data Distributions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:440-445 [Conf]
    
75. Saraju P. Mohanty, N. Ranganathan
    Energy Efficient Scheduling for Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:446-451 [Conf]
    
76. Ashok K. Murugavel, N. Ranganathan
    A Game-Theoretic Approach for Binding in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:452-0 [Conf]
    
77. Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:461-466 [Conf]
    
78. Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey
    High-level Synthesis of Multi-process Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:467-473 [Conf]
    
79. G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja
    Graph Transformations for Improved Tree Height Reduction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:474-479 [Conf]
    
80. Keith S. Vallerio, Niraj K. Jha
    Task Graph Extraction for Embedded System Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:480-0 [Conf]
    
81. M. Jagadesh Kumar, D. Venkateshrao
    A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:489-492 [Conf]
    
82. Alejandro F. González, Pinaki Mazumder
    Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:493-492 [Conf]
    
83. Abhisek Dixit, V. Ramgopal Rao
    A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:499-503 [Conf]
    
84. Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri
    A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and Temperature. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:504-506 [Conf]
    
85. Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi, P. K. Ghosh
    Synthesis Of Programmable Current Mode Linear Analog Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:507-512 [Conf]
    
86. Geun Rae Cho, Tom Chen
    On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:513-0 [Conf]
    
87. Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
    A Low Power-Delay Product Page-Based Address Bus Coding Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:521-526 [Conf]
    
88. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:527-532 [Conf]
    
89. Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz
    GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:533-538 [Conf]
    
90. Saraju P. Mohanty, N. Ranganathan
    A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:539-545 [Conf]
    
91. Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang
    Low-Energy BIST Design for Scan-based Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:546-551 [Conf]
    
92. Santanu Chattopadhyay, Naveen Choudhary
    Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:552-0 [Conf]
    
93. Kiran Puttegowda, William Worek, Nicholas Pappas, Anusha Dandapani, Peter Athanas, Allan Dickerman
    A Run-Time Reconfigurable System for Gene-Sequence Searching. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:561-566 [Conf]
    
94. Wu Jigang, Thambipillai Srikanthan
    A Run-time Reconfiguration Algorithm for VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:567-572 [Conf]
    
95. T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravi Kumar
    Optimal Code and Data Layout in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:573-578 [Conf]
    
96. Pao-Ann Hsiung, Feng-Shi Su
    Synthesis of Real-Time Embedded Software by Timed Quasi-Static Scheduling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:579-584 [Conf]
    
97. Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar
    SoC Synthesis with Automatic Hardware Software Interface Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:585-0 [Conf]