Conferences in DBLP

VLSI Design (vlsid)
1994 (conf/vlsid/1994)

1. Joseph B. Costello
   On the Brink of a New Era in VLSI Design. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:3- [Conf]
   
2. Pallab K. Chatterjee
   Gigachip Technology and the Signal Processing Revolution. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:4- [Conf]
   
3. Ahmed Hemani, Börje Karlsson, Mats Fredriksson, Kurt Nordqvist, Björn Fjellborg
   Application of High-Level Synthesis in an Industrial Project. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:5-10 [Conf]
   
4. Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi
   An Empirical Study on the Effects of Physical Design in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:11-16 [Conf]
   
5. Samit Chaudhuri, Robert A. Walker
   ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:17-20 [Conf]
   
6. A. R. Naseer, M. Balakrishnan, Anshul Kumar
   FAST: FPGA Targeted RTL Structure Synthesis Technique. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:21-24 [Conf]
   
7. David J. Kolson, Nikil D. Dutt, Alexandru Nicolau
   Ultra Fine-Grain Template-Driven Synthesis. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:25-28 [Conf]
   
8. Sharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester
   Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:29-32 [Conf]
   
9. Abhaya Asthana, Mike Laznovsky, Boyd Mathews
   SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:33-38 [Conf]
   
10. C. V. Ramamoorthy, Vikram Vij
    CM-SIM: A Parallel Circuit Simulator on a Distributed Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:39-44 [Conf]
    
11. Prathima Agrawal, Sanjay Goil, Sally Liu, John A. Trotter
    Parallel Model Evaluation for Circuit Simulation on the PACE Multiprocessor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:45-48 [Conf]
    
12. Dharmavani Bhagavathi, Stephan Olariu, James L. Schwing, Jingyuan Zhang
    Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:49-52 [Conf]
    
13. Dundar Dumlugol, Don Webber, Rajeev Madhavan
    Analog Modeling Using Event-Driven HDL's. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:53-56 [Conf]
    
14. Qingjian Yu, Omar Wing
    A SPICE Model of RLGC Transmission Line with Error Control. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:57-60 [Conf]
    
15. Naim Ben Hamida, Bozena Kaminska
    Multiple Fault Testing in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:61-66 [Conf]
    
16. Bapiraju Vinnakota, Ramesh Harjani
    The Design of Analog Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:67-70 [Conf]
    
17. Joydeep Ghosh, Patrick LaCour, Spence Jackson
    OTA Based Neural Network Architectures with On-Chip Tuning of Synapses. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:71-76 [Conf]
    
18. Debabrata Ghosh, S. K. Nandy, K. Parthasarathy
    TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:77-82 [Conf]
    
19. Keshab K. Parhi
    Calculation of Minimum Number of Registers in Arbitrary Life Time Chart. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:83-86 [Conf]
    
20. Arup K. Bhattacharya, Syed S. Haider
    A VLSI Architecture of an Inverse Discrete Cosine Transform. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:87-90 [Conf]
    
21. Heonchul Park, Viktor K. Prasanna
    A Fast Algorithm for Performing Vector Quantization and its VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:91-94 [Conf]
    
22. Debabrata Ghosh, Shamik Sural, S. K. Nandy
    A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:95-100 [Conf]
    
23. Shang-E Tai, Debashis Bhattacharya
    A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:101-106 [Conf]
    
24. C. P. Ravikumar, H. Rasheed
    Simulated Annealing for Target-Oriented Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:107-112 [Conf]
    
25. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    A Test Function Architecture for Interconnected Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:113-116 [Conf]
    
26. Md. Abdul Mottalib, P. Dasgupta
    A Bist PLA Design for High Fault Coverage and Testing by an Interleavingly Crosspoint Counting. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:117-122 [Conf]
    
27. Harry Hengster, Rolf Drechsler, Bernd Becker
    Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:123-126 [Conf]
    
28. Keumog Ahn, Sartaj Sahni
    Flipping Modules to Improve Circuit Performance and Routability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:127-132 [Conf]
    
29. Jens Lienig, Krishnaiyan Thulasiraman
    A New Genetic Algorithm for the Channel Routing Problem. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:133-136 [Conf]
    
30. Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani
    High Performance Over-the-Cell Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:137-142 [Conf]
    
31. Siddharth Bhingarde, Rafay Khawaja, Anand Panyam, Naveed A. Sherwani
    Over-the-Cell Routing Algorithms for Industrial Cell Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:143-148 [Conf]
    
32. Paul Molitor, Uwe Sparmann, Dorothea Wagner
    Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already Generated. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:149-154 [Conf]
    
33. Pradip K. Jha, Nikil D. Dutt
    Rapid Technology Projection for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:155-158 [Conf]
    
34. Yinghua Min, Yutang Zhou, Zhongcheng Li, Cheng Ye, Yuqi Pan
    Behavioral Design and Prototyping of a Fail-Safe System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:159-162 [Conf]
    
35. Ashutosh Majumdar, Minjoong Rim, Rajiv Jain, Renato De Leone
    BINET: An Algorithm for Solving the Binding Problem. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:163-168 [Conf]
    
36. S. Nandi, Vamsi Boppana, Parimal Pal Chaudhuri
    A CAD Tool for Design of On-Chip Store & Generate Scheme. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:169-174 [Conf]
    
37. Neeta Ganguly, Vijay Pitchumani
    HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:175-178 [Conf]
    
38. Sreejit Chakravarty, Sivaprakasam Suresh
    I_DDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:179-182 [Conf]
    
39. S. Hwang, Rochit Rajsuman, Scott Davidson
    I_DDQ Detection of CMOS Bridging Faults by Stuck-At Fault Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:183-186 [Conf]
    
40. Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong
    The Effect of Built-In Current Sensors (BICS) on Operational and Test Performance. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:187-190 [Conf]
    
41. S. M. Aziz, W. A. J. Waller
    On Testability of Differential Split-Level CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:191-196 [Conf]
    
42. K. Biswas, S. Rai
    Testable Realizations of CMOS Combinatorial Circuits for Voltage and Current Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:197-202 [Conf]
    
43. Reena Agarwal, Indranil Sengupta
    On the Synthesis of Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:203-206 [Conf]
    
44. Tanuj Bagchi, Sajal K. Das
    An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:207-210 [Conf]
    
45. Henrik Esbensen, Pinaki Mazumder
    SAGA: A Unification of the Genetic Algorithm with Simulated Annealing and its Application to Macro-Cell Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:211-214 [Conf]
    
46. Cyrus Bamji, Jonathan Allen
    GLOVE: A Graph-Based Layout Verifier. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:215-220 [Conf]
    
47. Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen
    A Sea-of-Gates Style FPGA Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:221-224 [Conf]
    
48. G. N. Rathna, S. K. Nandy, K. Parthasarathy
    A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:225-228 [Conf]
    
49. A. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal
    High Speed Digital Filtering on SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:229-232 [Conf]
    
50. Mahesh Mehendale
    Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:233-236 [Conf]
    
51. Amit Chowdhary, Dinesh Bhatia
    Detailed Routing of Multi-Terminal Nets in FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:237-242 [Conf]
    
52. Hemant Kanakia
    A Switch-Memory Chip for Packet Switching at Gigabits per Second. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:243-246 [Conf]
    
53. V. Keshava Murthy, K. Madhu Kumar, Mallikarjun B. Vani, D. Jagadish Kumar, C. S. Mohan, B. S. Prasanna
    A 2Kx1K Space Switch ASIC for Use in Digital Exchanges. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:247-250 [Conf]
    
54. Arunita Jaekel, Subir Bandyopadhyay, Abhijit Sengupta
    Laout Influenced Factorization of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:251-254 [Conf]
    
55. Irith Pomeranz, Sudhakar M. Reddy
    On Determining Symmetries in Inputs of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:255-260 [Conf]
    
56. Anantha Chandrakasan, Mani B. Srivastava, Robert W. Brodersen
    Energy Efficient Programmable Computation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:261-264 [Conf]
    
57. Abhijit Chatterjee, Rabindra K. Roy
    Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:265-270 [Conf]
    
58. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
    Power Constraint Scheduling of Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:271-274 [Conf]
    
59. Indradeep Ghosh, Bandana Majumdar
    Design of an Application Specific VLSI Chip for Image Rotation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:275-278 [Conf]
    
60. P. Pal Chowdhury, R. Barua
    Cellular Automata Based VLSI Architecture for Computing Multiplication and Inverses in GF (2^m). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:279-282 [Conf]
    
61. Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:283-286 [Conf]
    
62. Feng-Ming Yang, Stefan Wolter, Rainer Laur
    VLSI Architecture for HDTV Motion Estimation Based on Block-Matching Algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:287-290 [Conf]
    
63. Mario Kovac, N. Ranganathan
    ACE: A VLSI Chip for Galois Field GF (2^m) Based Exponentiation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:291-296 [Conf]
    
64. Dong Xiang, Dao-zheng Wei
    An Optimal Design for Parallel Test Generation Based on Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:297-300 [Conf]
    
65. Mohamed Jamoussi, Bozena Kaminska
    Data Path Testability Evaluation via Functional Testability Measures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:301-306 [Conf]
    
66. P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal
    An Improved Deductive Fault Simulator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:307-310 [Conf]
    
67. Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi
    On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:311-314 [Conf]
    
68. Mahesh A. Iyer, Miron Abramovici
    Low-Cost Redundancy Identification for Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:315-318 [Conf]
    
69. G. Hari Rama Krishna, Nirmal B. Chakrabarti, Swapna Banerjee
    Finite Element Analysis of SIGe npn HBT. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:319-322 [Conf]
    
70. Srikanth Natarajan, Debapriya Sahu, Sattam Dasgupta
    nOHM - A Multi-Process Device Synthesis Tool for Lateral DMOS Structures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:323-327 [Conf]
    
71. Shuvendu K. Lahiri, M. K. Das, A. Das Gupta, I. Manna
    3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold Voltage. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:328-332 [Conf]
    
72. M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi
    Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects in VLSI Processing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:333-338 [Conf]
    
73. A. Bandyopadhyay, P. R. Verma, A. B. Bhattacharyya, M. J. Zarabi
    LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:339-342 [Conf]
    
74. V. K. Anuradha, V. Visvanathan
    A CORDIC Based Programmable DXT Processor Array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:343-348 [Conf]
    
75. Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori
    Hierarchical Reconfiguration of VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:349-352 [Conf]
    
76. Emmanuel Casseau, Dominique Degrugillier
    A Linear Systolic Array for LU Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:353-358 [Conf]
    
77. Manoj Franklin, Kewal K. Saluja
    An Algorithm to Test Reconfigured RAMs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:359-364 [Conf]
    
78. Kanad Ghose, V. Anand Dharmaraj
    Response Pipelined CAM Chips: The First Generation and Beyond. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:365-368 [Conf]
    
79. Mahesh Mehendale, Biswadip Mitra
    An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:369-372 [Conf]
    
80. Chunduri Rama Mohan, Partha Pratim Chakrabarti
    A New Approach to Synthesis of PLA-Based FSM's. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:373-378 [Conf]
    
81. José C. Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto
    Bitwise Encoding of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:379-382 [Conf]
    
82. Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
    Synthesis of Initializable Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:383-388 [Conf]
    
83. I. Chakrabarti, Dilip Sarkar
    Mechanical Identification of Inductive Properties During Verification of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:389-394 [Conf]
    
84. Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti, S. C. De Sarkar
    Multiobjective Search in VLSI Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:395-400 [Conf]
    
85. James Sienicki, Michael L. Bushnell, Sandip Parikh
    Graphical Methodology Language for CAD Frameworks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:401-406 [Conf]
    
86. Santonu Sarkar, Anupam Basu
    An Object Oriented Environment for Modeling and Synthesis of Hardware Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:407-412 [Conf]
    
87. Mourad B. Takla, Donald W. Bouldin, Daniel B. Koch
    Early Exploration of the Multi-Dimensional VLSI Design Space. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:413-416 [Conf]
    
88. Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
    Verification of Circuits Described in VHDL through Extraction of Design Intent. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:417-420 [Conf]