Conferences in DBLP
Srivaths Ravi , Stefan Mangard Tutorial T1: Designing Secure SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] S. Sundar Kumar Iyer , Vivek Subramanian Tutorial T2: Organic Electronics: Technology, Devices, Circuits, and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Subhomoy Chattopadhyay , Rakesh Patel Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob A. Abraham , Daniel G. Saab Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Tiwari , Raj S. Mitra , Manu Chopra , Alok Jain Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting. [Citation Graph (0, 0)][DBLP ] Conf ] Nikil Dutt , Kaustav Banerjee , Luca Benini , Kanishka Lahiri , Sudeep Pasricha Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. [Citation Graph (0, 0)][DBLP ] Conf ] Sarma B. K. Vrudhula , Sarvesh Bhardwaj Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Beyne Tutorial T7A: Advanced IC Packaging. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Gupta , Taranjit Kukal , Alok Tripathi , Raja Mitra , Ashish Patni , Siddarth Shetty Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod Kathail , Shail Aditya , Craig Gleason , Nagesh Chatekar Tutorial T8A: Automated Application Engine Synthesis from C Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Samarjit Chakraborty , Abhik Roychoudhury Tutorial T8B: Performance Debugging of Complex Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Puranjoy Bhattacharya Tutorial IND1A: NeXperia - A Versatile Configurable Platform for Home and Mobile Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Uma Maheswar Rao , Suneel Sinha , Naveen Shenoy Tutorial IND1B: Realtime Operating Systems for Embedded Systems Development. [Citation Graph (0, 0)][DBLP ] Conf ] Parimal Patel Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] C. J. Clark Tutorial IND2B: Structured Embedded Configuration and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Wim Roelandts Creating a Culture of Innovation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Horowitz Scaling, Power and the Future of CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Tiwari Nanoelectronics Device Technologies: CMOS, Beyond and the Mysterious Case of Ockham's Razor. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad Bahai Where Analog meets Digital and Beyond. [Citation Graph (0, 0)][DBLP ] Conf ] Ajith Amerasekera Concurrent Optimization of Technology and Design for Nano CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto L. Sangiovanni-Vincentelli Reasoning about the Trends and Challenges of Engineering Design Automation. [Citation Graph (0, 0)][DBLP ] Conf ] J. Augusto de Oliveira Nexperia Computing Architecture for Connected Consumer Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Guerrieri Convergence of Nanoelectronics and Living Cells: A New Frontier for Diagnostics and Therapy? [Citation Graph (0, 0)][DBLP ] Conf ] Rene Penning de Vries Systems, Nano-technology and SiP. [Citation Graph (0, 0)][DBLP ] Conf ] Zhaohui Fu , Sharad Malik Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Shobha Vasudevan , Vinod Viswanath , Jacob A. Abraham Efficient Microprocessor Verification using Antecedent Conditioned Slicing. [Citation Graph (0, 0)][DBLP ] Conf ] Malay K. Ganai , Akira Mukaiyama , Aarti Gupta , Kazutoshi Wakabayashi Synthesizing "Verification Aware" Models: Why and How? [Citation Graph (0, 0)][DBLP ] Conf ] S. K. Panda , Arnab Roy , P. P. Chakrabarti , Rajeev Kumar Simulation Based Verification using Temporally Attributed Boolean Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Vishnu C. Vimjam , Michael S. Hsiao Explicit Safety Property Strengthening in SAT-based Induction. [Citation Graph (0, 0)][DBLP ] Conf ] Görschwin Fey , Tim Warode , Rolf Drechsler Reusing Learned Information in SAT-based ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Feihui Li , Guilin Chen , Mahmut T. Kandemir , Ozcan Ozturk , Mustafa Karaköy , R. Ramanarayanan , Balaji Vaidyanathan A Process Scheduler-Based Approach to NoC Power Management. [Citation Graph (0, 0)][DBLP ] Conf ] Ranjani Sridharan , Rabi N. Mahapatra Analysis of RealTime Embedded Applications in the Presence of a Stochastic Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Pravanjan Choudhury , P. P. Chakrabarti , Rajeev Kumar Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Sayak Ray , Pallab Dasgupta , P. P. Chakrabarti A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Balaji Vaidyanathan , Wei-Lun Hung , Feng Wang 0004 , Yuan Xie , Narayanan Vijaykrishnan , Mary Jane Irwin Architecting Microprocessor Components in 3D Design Space. [Citation Graph (0, 0)][DBLP ] Conf ] Sanghoan Chang , Gwan Choi Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjiv Kumar Mangal , Raghavendra B. Deshmukh , Rahul M. Badghare , R. M. Patrikar FPGA Implementation of Low Power Parallel Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Rohit Pandey , Michael L. Bushnell Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. [Citation Graph (0, 0)][DBLP ] Conf ] Sharath Jayaprakash , Nihar R. Mahapatra Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. [Citation Graph (0, 0)][DBLP ] Conf ] R. Bagheri , A. Mirzaei , S. Chehrazi , A. A. Abidi Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Khawshe , Pravin V. Kumar , Renu Rangnekar , Kapil Vyas , Kashi Prabu , Mahabaleshwara , Manish Jain , Navin Mishra , Abhijit Abhyankar A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL. [Citation Graph (0, 0)][DBLP ] Conf ] Shaikh K. Alam A 2 GHz Low Power Down-conversion Quadrature Mixer in 0.18-µm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Jagdish Nayayan Pandey , Sudhir S. Kudva , Bharadwaj Amrutur A Low Power Frequency Multiplication Technique for ZigBee Transciever. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Mandal , T. K. Bhattacharyya 7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Wang 0004 , Yuan Xie , R. Rajaraman , Balaji Vaidyanathan Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. [Citation Graph (0, 0)][DBLP ] Conf ] Hamed Aminzadeh , Mohammad Danaie , Reza Lotfi Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling Model. [Citation Graph (0, 0)][DBLP ] Conf ] Yogesh Singh Chauhan , Francois Krummenacher , Renaud Gillon , Benoit Bakeroot , Michel J. Declercq , Adrian M. Ionescu A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Deblina Sarkar , Samiran Ganguly , Deepanjan Datta , A. Ananda Prasad Sarab , Sudeb Dasgupta Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] M. Jagadesh Kumar , Vivek Venkataraman , Susheel Nawal Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Elias Kougianos , Saraju P. Mohanty Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Huiying Yang , Ranga Vemuri Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Chaitanya Sathe , Santanu Mahapatra Modeling and Analysis of Noise Margin in SET Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Soumyaroop Roy , Srinivas Katkoori , Nagarajan Ranganathan A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Taylan Yemliha , Guangyu Chen , Ozcan Ozturk , Mahmut T. Kandemir , Vijay Degalahal Compiler-Directed Code Restructuring for Operating with Compressed Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Ozcan Ozturk , Vijay Degalahal Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings. [Citation Graph (0, 0)][DBLP ] Conf ] Neeraj Goel , Anshul Kumar , Preeti Ranjan Panda Power Reduction in VLIW Processor with Compiler Driven Bypass Network. [Citation Graph (0, 0)][DBLP ] Conf ] Rakesh Nalluri , Rohan Garg , Preeti Ranjan Panda Customization of Register File Banking Architecture for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Sameer D. Sahasrabuddhe , Hakim Raja , Kavi Arya , Madhav P. Desai AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Liping Xue , Mahmut T. Kandemir , Guilin Chen , Feihui Li , Ozcan Ozturk , R. Ramanarayanan , Balaji Vaidyanathan Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Dobhal , Vishal Khandelwal , Ankur Srivastava Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes. [Citation Graph (0, 0)][DBLP ] Conf ] Srinath R. Naidu Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vineet Wason , Rajeev Murgai , William W. Walker An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ratnakar Goyal , Sachin Shrivastava , Harindranath Parameswaran , Parveen Khurana Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Kumar , Krishnendu Chakrabarty , Chunduri Rama Mohan An ECO Technique for Removing Crosstalk Violations in Clock Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Boyan Semerdjiev , Dimitrios Velenis Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Suchismita Roy , P. P. Chakrabarti , Pallab Dasgupta Bounded Delay Timing Analysis Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Keivan Navi , Omid Kavehie , Mahnoush Rouholamini , Amir Sahafi , Shima Mehrabi A Novel CMOS Full Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Roshan Weerasekera , Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen Delay-Balanced Smart Repeaters for On-Chip Global Signaling. [Citation Graph (0, 0)][DBLP ] Conf ] Jon Alfredsson , Snorre Aunet , Bengt Oelmann Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Gongqiong Li , Zhaolin Li Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Sreehari Veeramachaneni , Kirthi M. Krishna , Lingamneni Avinash , Reddy Puppala Sreekanth , M. B. Srinivas Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. [Citation Graph (0, 0)][DBLP ] Conf ] Claas Cornelius , Frank Grassert , Siegmar Koppe , Dirk Timmermann Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Jain , Jais Abraham , Srinivas Kumar Vooka , Sumant Kale , Amit Dutta , Rubin A. Parekhji Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Kedarnath J. Balakrishnan Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding. [Citation Graph (0, 0)][DBLP ] Conf ] V. R. Devanathan , C. P. Ravikumar , V. Kamakoti Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Rajamani Sethuram , Seongmoon Wang , Srimat T. Chakradhar , Michael L. Bushnell Zero Cost Test Point Insertion Technique for Structured ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Subir K. Roy , Rubin A. Parekhji Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Kenji Asano , Junji Kitamichi , Kenichi Kuroda Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Senthil Kumar Lakshmanan , Peter Tawdross , Andreas König Towards Generic On-the-Fly Reconfigurable Sensor Electronics for Embedded System- First Measurement Results of Reconfigurable Folded. [Citation Graph (0, 0)][DBLP ] Conf ] Jorgen Peddersen , Sri Parameswaran Energy Driven Application SelfAdaptation. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip H. Jones , Young H. Cho , John W. Lockwood Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Dhiren M. Parmar , M. Sarma , Debasis Samanta A Novel Approach to Domino Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] K. Najeeb , Karthik Gururaj , V. Kamakoti , Vivekananda M. Vedula Controllability-driven Power Virus Generation for Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fu-Chiung Cheng , Shu-Ming Chang , Chi-Huam Shieh Detection and Generation of Self-Timed Pipelines from High Level Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Balasubramanian Sethuraman , Ranga Vemuri A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Hendrik F. Hamann , Alan J. Weger , James Lacey , Zhigang Hu , Pradip Bose , Erwin Cohen , Jamil A. Wakil Temperature-limited microprocessors: Measurements and design implications. [Citation Graph (0, 0)][DBLP ] Conf ] Qianneng Zhou , FengChang Lai , Yongsheng Wang On-Chip Voltage Down Converter Based on Moderate Inversion for Low- Power VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Yuanlin Lu , Vishwani D. Agrawal Statistical Leakage and Timing Optimization for Submicron Process Variation. [Citation Graph (0, 0)][DBLP ] Conf ] Akepati Sravan , Sujan Kundu , Ajit Pal Low Power Sensor Node for a Wireless Sensor Network. [Citation Graph (0, 0)][DBLP ] Conf ] Yijun Liu , Zhenkun Li , Pinghua Chen , Guangcong Liu Power-Efficient Asynchronous Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan Bahukudumbi , Krishnendu Chakrabarty Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Sreekumar V. Kodakara , Deepak Mathaikutty , Ajit Dingankar , Sandeep K. Shukla , David J. Lilja Model Based Test Generation for Microprocessor Architecture Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Nitin Yogi , Vishwani D. Agrawal Spectral RTL Test Generation for Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] H. Rahaman , Jimson Mathew , Dhiraj K. Pradhan Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). [Citation Graph (0, 0)][DBLP ] Conf ] Suresh Kumar Devanathan , Michael L. Bushnell Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Kalyana R. Kantipudi , Vishwani D. Agrawal A Reduced Complexity Algorithm for Minimizing N-Detect Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Loganathan Lingappan , Vijay Gangaram , Niraj K. Jha Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Bansal , Kanishka Lahiri , Anand Raghunathan Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Mathur , Sourav Roy , Rajat Bhatia , Arup Chakraborty , Vijay Bhargava , Jatin Bhartia JouleQuest: An Accurate Power Model for the StarCore DSP Platform. [Citation Graph (0, 0)][DBLP ] Conf ] T. S. Rajesh Kumar , C. P. Ravikumar , R. Govindarajan MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Tsun Sun , Zoran Salcic Modeling RTOS for Reactive Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] G. Hazari , Madhav P. Desai , H. Kasture On the Impact of Address Space Assignment on Performance in Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Masoud Daneshtalab , A. Pedram , Mohammad Hossein Neishaburi , M. Riazati , Ali Afzali-Kusha , Simak Mohammadi Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections. [Citation Graph (0, 0)][DBLP ] Conf ] Nagaraju Pothineni , Anshul Kumar , Kolin Paul Application Specific Datapath Extension with Distributed I/O Functional Units. [Citation Graph (0, 0)][DBLP ] Conf ] Aseem Gupta , Nikil D. Dutt , Fadi J. Kurdahi , Kamal S. Khouri , Magdy S. Abadir STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Subramanian Rajagopalan , Shabbir H. Batterywala A 3-dimensional FEM Based Resistance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Dobhal , Vishal Khandelwal , Azadeh Davoodi , Ankur Srivastava Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. [Citation Graph (0, 0)][DBLP ] Conf ] Saraju P. Mohanty , Elias Kougianos Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ashesh Rastogi , Wei Chen , Alodeep Sanyal , Sandip Kundu An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. [Citation Graph (0, 0)][DBLP ] Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Anupam Chattopadhyay , Diandian Zhang , David Kammler , Ernst Martin Witte Power-efficient Instruction Encoding Optimization for Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Nenggan Zheng , Zhaohui Wu , Man Lin , Qijia Wang Interpreting and Extending an Analytical Battery Model Using an Iterative Computation Method. [Citation Graph (0, 0)][DBLP ] Conf ] Masaaki Iijima , Masayuki Kitamura , Masahiro Numa , Akira Tada , Takashi Ipposhi Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Qikai Chen , Arjun Guha , Kaushik Roy An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. [Citation Graph (0, 0)][DBLP ] Conf ] Sayeed A. Badrudduza , Giby Samson , Lawrence T. Clark LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability. [Citation Graph (0, 0)][DBLP ] Conf ] Lava P. Kumar , Baquer Mazhari Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode. [Citation Graph (0, 0)][DBLP ] Conf ] Duk-Hyung Lee , Dong-Kone Kwak , Kyeong-Sik Min Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs. [Citation Graph (0, 0)][DBLP ] Conf ] K. R. Viveka , Abhilasha Kawle , Bharadwaj Amrutur Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Xu , Krishnendu Chakrabarty , Fei Su Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips. [Citation Graph (0, 0)][DBLP ] Conf ] Jyi-Tsong Lin , Yi-Chuen Eng , Tai-Yi Lee , Kao-Cheng Lin Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Mazor , Michael L. Bushnell , David J. Mulligan , Richard J. Blaikie Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv V. Joshi , Keunwoo Kim , Richard Q. Williams , Edward J. Nowak , Ching-Te Chuang A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Jiajin Tu , Jian Chen , Lizy K. John Hardware Efficient Piecewise Linear Branch Predictor. [Citation Graph (0, 0)][DBLP ] Conf ] Rajamani Sethuram , Omar I. Khan , Hari Vijay Venkatanarayanan , Michael L. Bushnell A Neural Net Branch Predictor to Reduce Power. [Citation Graph (0, 0)][DBLP ] Conf ] Soumyajit Dey , Monu Kedia , Niket Agarwal , Anupam Basu Embedded Support Vector Machine : Architectural Enhancements and Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Asral Bahari , Tughrul Arslan , Ahmet T. Erdogan Interframe Bus Encoding Technique for Low Power Video Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Bhunia , Saibal Mukhopadhyay , Kaushik Roy Process Variations and Process-Tolerant Design. [Citation Graph (0, 0)][DBLP ] Conf ] Debayan Bhaduri , Sandeep K. Shukla , Paul Graham , Maya Gokhale Scalable techniques and tools for reliability analysis of large circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Maryam Ashouei , Muhammad M. Nisar , Abhijit Chatterjee , Adit D. Singh , Abdulkadir Utku Diril Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. [Citation Graph (0, 0)][DBLP ] Conf ] K. Ramakrishnan , S. Suresh , Narayanan Vijaykrishnan , Mary Jane Irwin Impact of NBTI on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Xiangning Yang , Eric F. Weglarz , Kewal K. Saluja On NBTI Degradation Process in Digital Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Matteo Giaconia , Marco Macchetti , Francesco Regazzoni , Kai Schramm Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes. [Citation Graph (0, 0)][DBLP ] Conf ] Kiran K. Gunnam , Gwan S. Choi , Mark B. Yeary A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Zahid Khan , Tughrul Arslan , John S. Thompson , Ahmet T. Erdogan Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems. [Citation Graph (0, 0)][DBLP ] Conf ] M. Sudhakar , Ramachandruni Venkata Kamala , M. B. Srinivas A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n). [Citation Graph (0, 0)][DBLP ] Conf ] J. H. Han , Ahmet T. Erdogan , Tughrul Arslan A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gefu Xu , Adit D. Singh Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kim T. Le , Dong Hyun Baik , Kewal K. Saluja Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Ayres , Michael L. Bushnell Analog Circuit Testing Using Auto Regressive Moving Average Models. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Kewal K. Saluja , Hiroshi Takahashi , Yuzo Takamatsu Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Satish Yada , Bharadwaj Amrutur , Rubin A. Parekhji Modified Stability Checking for On-line Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Santiago Remersaro , Xijiang Lin , Sudhakar M. Reddy , Irith Pomeranz , Janusz Rajski Low Shift and Capture Power Scan Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Functional Broadside Tests with Different Levels of Reachability. [Citation Graph (0, 0)][DBLP ] Conf ] Edward Flanigan , Rajsekhar Adapa , Hailong Cui , Michael Laisne , Spyros Tragoudas , Tsvetomir Petrov Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Jain , Preeti Ranjan Panda Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Himanshu Patel , Sanjay Trivedi , R. Neelkanthan , V. R. Gujraty A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Rupak Samanta , Rabi N. Mahapatra An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Feng He , Meng-Lian Zhao , Chi-Ying Tsui , Zhi-Gang Mao A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Chitranjan K. Singh , Sushma Honnavara Prasad , Poras T. Balsara VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Debdeep Mukhopadhyay , Pallavi Joshi , Dipanwita Roy Chowdhury An Efficient Design of Cellular Automata Based Cryptographically Robust One-Way Function. [Citation Graph (0, 0)][DBLP ] Conf ] V. Amudha , B. Venkataramani , R. Vinoth kumar , S. Ravishankar SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System. [Citation Graph (0, 0)][DBLP ] Conf ] Karthik Baddam , Mark Zwolinski Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure. [Citation Graph (0, 0)][DBLP ] Conf ] Gaurav Trivedi , Madhav P. Desai , H. Narayanan Parallelization of DC Analysis through Multiport Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Gaurav Trivedi , Sumit Punglia , H. Narayanan Application of DC Analyzer to Combinatorial Optimization Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Debjit Sinha , Jianfeng Luo , Subramanian Rajagopalan , Shabbir H. Batterywala , Narendra V. Shenoy , Hai Zhou Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Venkataraman , Jiang Hu A Placement Methodology for Robust Clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Sankar P. Debnath , Ganesh P. Kumar 0002 , S. Jairam Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc. [Citation Graph (0, 0)][DBLP ] Conf ] Pritha Banerjee , Susmita Sur-Kolay , Arijit Bishnu Floorplanning in Modern FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Tai Yan , Bo-Yi Chiang Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Reid R. Harrison , Paul T. Watkins , Ryan J. Kier , Daniel J. Black , Robert O. Lovejoy , Richard A. Normann , Florian Solzbacher Design and Testing of an Integrated Circuit for Multi-Electrode Neural Recording. [Citation Graph (0, 0)][DBLP ] Conf ] S. M. Rezaul Hasan A PMOS-diode Differential Body-driven Offset compensated 0.5V. [Citation Graph (0, 0)][DBLP ] Conf ] U. K. Vijay , Amrutur Bharadwaj Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Kumar Wadhwa , Deeya Muhury , Krishna Thakur Programmable Digital Frequency Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Pradipta Patra , Amit Patra , Debaprasad Kastha On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu A. Bhalerao , Abhishek V. Chaudhary , Rajendra M. Patrikar A CMOS Low Voltage Charge Pump. [Citation Graph (0, 0)][DBLP ] Conf ] 