Conferences in DBLP
David E. Long , Mahesh A. Iyer , Miron Abramovici Identifying sequentially untestable faults using illegal states. [Citation Graph (0, 0)][DBLP ] Conf ] Srimat T. Chakradhar , Steven G. Rothweiler Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. [Citation Graph (0, 0)][DBLP ] Conf ] Mark C. Hansen , John P. Hayes High-level test generation using physically-induced faults. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda , Enzo Veiluva A portable ATPG tool for parallel and distributed systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Gizopoulos , Dimitris Nikolos , Antonis M. Paschalis Testing combinational iterative logic arrays for realistic faults. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Balivada , Yatin Vasant Hoskote , Jacob A. Abraham Verification of transient response of linear analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Diego Vázquez , Adoración Rueda , José L. Huertas A solution for the on-line test of analog ladder filters. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled Saab , Bozena Kaminska , Bernard Courtois , Marcelo Lubaszewski Frequency-based BIST for analog circuit testin. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter A low cost 100 MHz analog test bus. [Citation Graph (0, 0)][DBLP ] Conf ] Lahouari Sebaa , Norm Gardner , Robert Neidorff , Rich Valley Self-test in a VCM driver chip. [Citation Graph (0, 0)][DBLP ] Conf ] Li-C. Wang , M. Ray Mercer , Sophia W. Kao , Thomas W. Williams On the decline of testing efficiency as fault coverage approaches 100%. [Citation Graph (0, 0)][DBLP ] Conf ] Peter C. Maxwell The use of IDDQ testing in low stuck-at coverage situations. [Citation Graph (0, 0)][DBLP ] Conf ] Vinay Dabholkar , Sreejit Chakravarty , J. Najm , Janak H. Patel Cyclic stress tests for full scan circuits. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Segura , M. Roca , D. Mateo , A. Rubio An approach to dynamic power consumption current testing of CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] J. Arguelles , M. J. Lopez , J. Blanco , M. Martínez , S. Bracho Iddt testing of continuous-time filters. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir On shrinking wide compressors. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele Signature analysis and aliasing for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shridhar K. Mukund , Edward J. McCluskey , T. R. N. Rao An apparatus for pseudo-deterministic testing. [Citation Graph (0, 0)][DBLP ] Conf ] Nilanjan Mukherjee , H. Kassab , Janusz Rajski , Jerzy Tyszer Arithmetic built-in self test for high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey A. Floyd , Matt Perry Real-time on-board bus testing. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Yotsuyanagi , Seiji Kajihara , Kozo Kinoshita Resynthesis for sequential circuits designed with a specified initial state. [Citation Graph (0, 0)][DBLP ] Conf ] Frank F. Hsu , Janak H. Patel A distance reduction approach to design for testability. [Citation Graph (0, 0)][DBLP ] Conf ] Ting-Yu Kuo , Chun-Yeh Liu , Kewal K. Saluja An optimized testable architecture for finite state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Mahsa Vahidi , Alex Orailoglu Testability metrics for synthesis of self-testable designs and effective test plans. [Citation Graph (0, 0)][DBLP ] Conf ] Xinli Gu RT level testability-driven partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , P. Huc , Yves Bertrand The concept of resistance interval: a new parametric model for realistic resistive bridging fault. [Citation Graph (0, 0)][DBLP ] Conf ] Ding Lu , Carol Q. Tong High level fault modeling of asynchronous circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Samy Makar , Edward J. McCluskey Checking experiments to test latches. [Citation Graph (0, 0)][DBLP ] Conf ] Víctor H. Champac , Joan Figueras Testability of floating gate defects in sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Lidén , Peter Dahlgren Switch-level modeling of transistor-level stuck-at faults. [Citation Graph (0, 0)][DBLP ] Conf ] Tapan J. Chakraborty , Vishwani D. Agrawal Simulation of at-speed tests for stuck-at faults. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Nair , Dong Sam Ha VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Riedel , Janusz Rajski Fault coverage analysis of RAM test algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Bogliolo , Maurizio Damiani , Piero Olivo , Bruno Riccò Reliability evaluation of combinational logic circuits by symbolic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Stroud , T. Raju Damarla Improving the efficiency of error identification via signature analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Samantha Edirisooriya , Geetani Edirisooriya Diagnosis of scan path failures. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Liu , Fabrizio Lombardi , José Salinas Diagnosis of interconnects and FPICs using a structured walking-1 approach. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Thibeault Detection and location of faults and defects using digital signal processing. [Citation Graph (0, 0)][DBLP ] Conf ] Sridhar Narayanan , Melvin A. Breuer Asynchronous multiple scan chain. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng Partial scan designs without using a separate scan clock. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Khoche , Erik Brunvand A partial scan methodology for testing self-timed circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Soufi , Yvon Savaria , Bozena Kaminska On the design of at-speed testable VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] O. A. Petlin , Stephen B. Furber Scan testing of micropipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Marcello Dalpasso , Michele Favalli , Piero Olivo Test pattern generation for I/sub DDQ/: increasing test quality. [Citation Graph (0, 0)][DBLP ] Conf ] Remata S. Reddy , Irith Pomeranz , Sudhakar M. Reddy , Seiji Kajihara Compact test generation for bridging faults under I/sub DDQ/ testing. [Citation Graph (0, 0)][DBLP ] Conf ] Udo Mahlstedt , Jürgen Alt , Matthias Heinitz CURRENT: a test generation system for I/sub DDQ/ testing. [Citation Graph (0, 0)][DBLP ] Conf ] Josep Rius , Joan Figueras Detecting I/sub DDQ/ defective CMOS circuits by depowering. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelino B. Santos , M. Simões , Isabel C. Teixeira , João Paulo Teixeira Test preparation for high coverage of physical defects in CMOS digital ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Matteo Sonza Reorda , Uwe Gläser , Heinrich Theodor Vierhaus Improving topological ATPG with symbolic techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Inoue , Hironori Maeda , Hideo Fujiwara A scheduling problem in test generation. [Citation Graph (0, 0)][DBLP ] Conf ] Andrej Zemva , Franc Brglez Detectable perturbations: a paradigm for technology-specific multi-fault test generation. [Citation Graph (0, 0)][DBLP ] Conf ] M. H. Konijnenburg , J. Th. van der Linden , A. J. van de Goor Compact test sets for industrial circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bapiraju Vinnakota , Nicholas J. Stessman Reducing test application time in scan design schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Kwang-Ting Cheng Generation of high quality tests for functional sensitizable paths. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Christian Landrault , Serge Pravossoudovitch , B. Rodriguez Diagnostic of path and gate delay faults in non-scan sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Harry Hengster , Rolf Drechsler , Bernd Becker On the application of local circuit transformations with special emphasis on path delay fault testability. [Citation Graph (0, 0)][DBLP ] Conf ] Imtiaz P. Shaik , Michael L. Bushnell Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . [Citation Graph (0, 0)][DBLP ] Conf ] Wuudiann Ke , Premachandran R. Menon Multifault testability of delay-testable circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nur A. Touba , Edward J. McCluskey Transformed pseudo-random patterns for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Mitrajit Chatterjee , Dhiraj K. Pradhan A novel pattern generator for near-perfect fault-coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Nadime Zacharia , Janusz Rajski , Jerzy Tyszer Decompression of test data using variable-length seed LFSRs. [Citation Graph (0, 0)][DBLP ] Conf ] Samir Lejmi , Bozena Kaminska , Bechir Ayari Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Günter Kemnitz Synthesis of locally exhaustive test pattern generators. [Citation Graph (0, 0)][DBLP ] Conf ] Samvel K. Shoukourian , Armen G. Kostanian , Valery A. Margarian , Ayman A. Ashour An approach for system tests design and its application. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Bogliolo , Maurizio Damiani Synthesis of combinational circuits with special fault-handling capabilitie. [Citation Graph (0, 0)][DBLP ] Conf ] B. Hamdi , H. Bederr , Michael Nicolaidis A tool for automatic generation of self-checking data paths. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Brown , Germán Gutiérrez , Reed Nelson , Chris VanKrevelen A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers. [Citation Graph (0, 0)][DBLP ] Conf ] Walter W. Weber , Adit D. Singh An experimental evaluation of the differential BICS for I/sub DDQ/ testing. [Citation Graph (0, 0)][DBLP ] Conf ] Joan Carletta , Christos A. Papachristou Structural constraints for circular self-test paths. [Citation Graph (0, 0)][DBLP ] Conf ] 