Conferences in DBLP
Nandu Tendolkar , Robert F. Molyneaux , Carol Pyron , Rajesh Raina At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:3-8 [Conf ] Narayanan Krishnamurthy , Andrew K. Martin , Magdy S. Abadir , Jacob A. Abraham Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:9-14 [Conf ] Wei-Cheng Lai , Angela Krstic , Kwang-Ting Cheng On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:15-22 [Conf ] Dimitris Gizopoulos , Nektarios Kranitis , Mihalis Psarakis , Antonis M. Paschalis , Yervant Zorian Low Power/Energy BIST Scheme for Datapaths. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:23-28 [Conf ] Fulvio Corno , Maurizio Rebaudengo , Matteo Sonza Reorda , Giovanni Squillero , Massimo Violante Low Power BIST via Non-Linear Hybrid Cellular Automata. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:29-34 [Conf ] Ranganathan Sankaralingam , Rama Rao Oruganti , Nur A. Touba Static Compaction Techniques to Control Scan Vector Power Dissipation. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:35-42 [Conf ] R. Dean Adams , Phil Shephard Iii Silicon-on-Insulator Technology Impacts on SRAM Testing. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:43-48 [Conf ] Byungwoo Choi , D. M. H. Walker Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:49-54 [Conf ] Lorena Anghel , Michael Nicolaidis , Issam Alzaher-Noufal Self-Checking Circuits versus Realistic Faults in Very Deep Submicron. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:55-66 [Conf ] Frank P. Higgins , Rajagopalan Srinivasan BSM2: Next Generation Boundary-Scan Master. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:67-72 [Conf ] Abhijit Jas , Bahram Pouya , Nur A. Touba Virtual Scan Chains: A Means for Reducing Scan Length in Cores. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:73-78 [Conf ] Jayabrata Ghosh-Dastidar , Nur A. Touba A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:79-88 [Conf ] Hugo Cheung , Sandeep K. Gupta A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:89-96 [Conf ] Jing-Jia Liou , Kwang-Ting Cheng , Deb Aditya Mukherjee Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:97-104 [Conf ] Chul Young Lee , D. M. H. Walker PROBE: A PPSFP Simulator for Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:105-112 [Conf ] Anshuman Chandra , Krishnendu Chakrabarty Test Data Compression for System-on-a-Chip Using Golomb Codes. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:113-120 [Conf ] A. Bommireddy , Jitendra Khare , Saghir A. Shaikh , S.-T. Su Test and Debug of Networking SoCs: A Case Study. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:121-126 [Conf ] Krishnendu Chakrabarty Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:127-136 [Conf ] Ramakrishna Voorakaranam , Abhijit Chatterjee Test Generation for Accurate Prediction of Analog Specifications. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:137-142 [Conf ] Jeongjin Roh , Jacob A. Abraham A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:143-148 [Conf ] Sule Ozev , Alex Orailoglu Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:149-156 [Conf ] Vivek Chickermane , Scott Richter , Carl Barnhart Integrating Logic BIST in VLSI Designs with Embedded Memories. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:157-164 [Conf ] Albrecht P. Stroele Synthesis for Arithmetic Built-In Self-Tes. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:165-170 [Conf ] Kwame Osei Boateng , Hiroshi Takahashi , Yuzo Takamatsu General BIST-Amenable Method of Test Generation for Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:171-178 [Conf ] M. S. Huetmaker RF/Analog Test of Circuits and Systems. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:179-182 [Conf ] Chao-Wen Tseng , Edward J. McCluskey , Xiaoping Shao , David M. Wu Cold Delay Defect Screening. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:183-188 [Conf ] Josep Altet , Antonio Rubio , E. Schaub , Stefan Dilhaire , Wilfrid Claeys Thermal Testing: Fault Location Strategies. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:189-194 [Conf ] Amy Germida , James F. Plusquellic Detection of CMOS Defects under Variable Processing Conditions. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:195-204 [Conf ] Xijiang Lin , Wu-Tung Cheng , Irith Pomeranz , Sudhakar M. Reddy SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:205-212 [Conf ] Markus Seuring , Krishnendu Chakrabarty Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:213-220 [Conf ] Hussain Al-Asaad , John P. Hayes ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:221-230 [Conf ] Seongwon Kim , Mani Soma , Dilip Risbud An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:231-236 [Conf ] Jan Arild Tofte , Chee-Kian Ong , Jiun-Lang Huang , Kwang-Ting (Tim) Cheng Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:237-246 [Conf ] Michel Renovell , Florence Azaïs , Serge Bernard , Yves Bertrand Hardware Resource Minimization for Histogram-Based ADC BIST. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:247-254 [Conf ] Li Chen , Sujit Dey DEFUSE: A Deterministic Functional Self-Test Methodology for Processors. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:255-262 [Conf ] Ankur Jain , Vamsi Boppana , Rajarshi Mukherjee , Jawahar Jain , Masahiro Fujita , Michael S. Hsiao Testing, Verification, and Diagnosis in the Presence of Unknowns. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:263-270 [Conf ] Katarzyna Radecka , Zeljko Zilic Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:271-280 [Conf ] A. J. van de Goor , Zaid Al-Ars Functional Memory Faults: A Formal Notation and a Taxonomy. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:281-290 [Conf ] Chi-Feng Wu , Chih-Tsun Huang , Kuo-Liang Cheng , Cheng-Wen Wu Simulation-Based Test Algorithm Generation for Random Access Memories. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:291-296 [Conf ] Jun Zhao , V. Swamy Irrinki , Mukesh Puri , Fabrizio Lombardi Detection of Inter-Port Faults in Multi-Port Static RAMs. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:297-304 [Conf ] Víctor H. Champac , Antonio Zenteno Detectability Conditions for Interconnection Open Defect. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:305-312 [Conf ] Srikanth Venkataraman , Scott Brady Drummonds A Technique for Logic Fault Diagnosis of Interconnect Open Defects. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:313-318 [Conf ] José Vicente Calvano , Vladimir Castro Alves , Marcelo Lubaszewski Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:319-324 [Conf ] T. W. Williams , Stephen K. Sunter How Should Fault Coverage Be Defined? [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:325-328 [Conf ] Bapiraju Vinnakota , André Ivanov Biomedical ICs: What is Different about Testing those ICs? [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:329-332 [Conf ] Manish Sharma , Janak H. Patel Bounding Circuit Delay by Testing a Very Small Subset of Paths. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:333-342 [Conf ] Ramesh C. Tekumalla On Test Set Generation for Efficient Path Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:343-348 [Conf ] Hans G. Kerkhoff , Mansour Shashaani , Manoj Sachdev A Low-Speed BIST Framework for High-Performance Circuit Testing. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:349-358 [Conf ] Laurent Bréhélin , Olivier Gascuel , Gilles Caraux , Patrick Girard , Christian Landrault Hidden Markov and Independence Models with Patterns for Sequential BIST. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:359-368 [Conf ] Ilker Hamzaoglu , Janak H. Patel Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:369-376 [Conf ] Grzegorz Mrugalski , Jerzy Tyszer , Janusz Rajski Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:377-388 [Conf ] Peter Wohl , Nathan Biggs P1450.1: STIL for the Simulation Environmen. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:389-394 [Conf ] Takahiro J. Yamaguchi , Masahiro Ishida , Mani Soma , Toshifumi Watanabe , Tadahiro Ohmi Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:395-402 [Conf ] Chauchin Su , Yue-Tsang Chen Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:403-410 [Conf ] Fulvio Corno , Matteo Sonza Reorda , Giovanni Squillero High-Level Observability for Effective High-Level ATPG. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:411-416 [Conf ] Valentin Muresan , Xiaojun Wang , Valentina Muresan , Mircea Vladutiu The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:417-422 [Conf ] Fabrizio Ferrandi , G. Fornara , Donatella Sciuto , G. Ferrara , Franco Fummi Testability Alternatives Exploration through Functional Testing. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:423-430 [Conf ] Claude Thibeault Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:431-438 [Conf ] Theo J. Powell , James R. Pair , Melissa St. John , Doug Counce Delta Iddq for Testing Reliability. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:439-443 [Conf ] Sri Jandhyala , Hari Balachandran , Manidip Sengupta , Anura P. Jayasumana Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:444-452 [Conf ] Subhasish Mitra , Nirmal R. Saxena , Edward J. McCluskey Fault Escapes in Duplex Systems. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:453-458 [Conf ] Yiorgos Makris , Ismet Bayraktaroglu , Alex Orailoglu Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:459-464 [Conf ] Subhasish Mitra , Edward J. McCluskey Word Voter: A New Voter Design for Triple Modular Redundant Systems. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:465-470 [Conf ] Fidel Muradali , André Ivanov Do I Need this Tool for My Chips to Work? [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:471-472 [Conf ] Melvin A. Breuer High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. [Citation Graph (0, 0)][DBLP ] VTS, 2000, pp:473-474 [Conf ]