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Conferences in DBLP

IEEE VLSI Test Symposium (vts)
1996 (conf/vts/1996)

  1. Nur A. Touba, Edward J. McCluskey
    Test point insertion based on path tracing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:2-8 [Conf]
  2. R. D. (Shawn) Blanton, John P. Hayes
    Design of a fast, easily testable ALU. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:9-16 [Conf]
  3. Fidel Muradali, Janusz Rajski
    A self-driven test structure for pseudorandom testing of non-scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:17-25 [Conf]
  4. Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Scan insertion criteria for low design impact. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:26-31 [Conf]
  5. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    Segment delay faults: a new fault model. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:32-41 [Conf]
  6. Diego Vázquez, José L. Huertas, Adoración Rueda
    Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:42-47 [Conf]
  7. Eric Felt, Alberto L. Sangiovanni-Vincentelli
    Optimization of analog IC test structures. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:48-53 [Conf]
  8. Michel Renovell, Florence Azaïs, Yves Bertrand
    The multi-configuration: A DFT technique for analog circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:54-59 [Conf]
  9. Mehdi Ehsanian, Bozena Kaminska, Karim Arabi
    A new digital test approach for analog-to-digital converter testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:60-65 [Conf]
  10. J. van Spaandonk, Tom A. M. Kevenaar
    Iterative test-point selection for analog circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:66-73 [Conf]
  11. Subhrajit Bhattacharya, Sujit Dey
    H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:74-80 [Conf]
  12. X. Wendling, R. Rochet, Régis Leveugle
    Standard and ROM-based synthesis of FSMs with control flow checking capabilities. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:81-86 [Conf]
  13. Robert B. Norwood, Edward J. McCluskey
    Synthesis-for-scan and scan chain ordering. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:87-92 [Conf]
  14. Yuan Lu, Irith Pomeranz
    Synchronization of large sequential circuits by partial reset. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:93-98 [Conf]
  15. M. Miegler, Werner Wolz
    Development of test programs in a virtual test environment. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:99-105 [Conf]
  16. Antoni Ferré, Joan Figueras
    On estimating bounds of the quiescent current for I/sub DDQ/ testin. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:106-111 [Conf]
  17. Anne E. Gattiker, Wojciech Maly
    Current signatures [VLSI circuit testing]. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:112-117 [Conf]
  18. Stephan P. Athan, David L. Landis, Sami A. Al-Arian
    A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:118-123 [Conf]
  19. Salvador Manich, Michael Nicolaidis, Joan Figueras
    Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:124-129 [Conf]
  20. Hari Balachandran, D. M. H. Walker
    Improvement of SRAM-based failure analysis using calibrated Iddq testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:130-137 [Conf]
  21. Egor S. Sogomonyan, Michael Gössel
    Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:138-144 [Conf]
  22. Cecilia Metra, Michele Favalli, Bruno Riccò
    Embedded two-rail checkers with on-line testing ability. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:145-150 [Conf]
  23. Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis
    An asynchronous totally self-checking two-rail code error indicator. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:151-156 [Conf]
  24. Steven S. Gorshe, Bella Bose
    A self-checking ALU design with efficient codes. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:157-161 [Conf]
  25. Vl. V. Saposhnikov, Alexej Dmitriev, Michael Gössel, V. V. Saposhnikov
    Self-dual parity checking-A new method for on-line testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:162-168 [Conf]
  26. Jean-Luis Dufour
    Safety computations in integrated circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:169-173 [Conf]
  27. Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs
    Full fault dictionary storage based on labeled tree encoding. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:174-179 [Conf]
  28. John W. Sheppard, William R. Simpson
    Improving the accuracy of diagnostics provided by fault dictionaries. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:180-185 [Conf]
  29. Masaru Sanada
    A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:186-191 [Conf]
  30. Sreejit Chakravarty
    A sampling technique for diagnostic fault simulation. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:192-197 [Conf]
  31. Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs
    Dynamic diagnosis of sequential circuits based on stuck-at faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:198-203 [Conf]
  32. Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi
    On the diagnosis of programmable interconnect systems: Theory and application. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:204-211 [Conf]
  33. Robert C. Aitken, J. Hutcheson, N. Murthy, Phil Nigh, Nicholas Sporck
    Volume Manufacturing - ICs and Boards: DFT to the Rescue? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:212-213 [Conf]
  34. Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik
    Is High Frequency Analog DFT Possible? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:214-215 [Conf]
  35. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
    Automatic test generation using genetically-engineered distinguishing sequences. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:216-223 [Conf]
  36. Krishna B. Rajan, David E. Long, Miron Abramovici
    Increasing testability by clock transformation (getting rid of those darn states). [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:224-230 [Conf]
  37. Robert H. Klenke, James H. Aylor, Joseph M. Wolf
    An analysis of fault partitioning algorithms for fault partitioned ATPG. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:231-239 [Conf]
  38. Martin Keim, Bernd Becker, Birgitta Stenner
    On the (non-)resetability of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:240-245 [Conf]
  39. Jalal A. Wehbeh, Daniel G. Saab
    Initialization of sequential circuits and its application to ATPG. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:246-253 [Conf]
  40. T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael
    Faulty chip identification in a multi chip module system. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:254-259 [Conf]
  41. Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan
    Low-cost diagnosis of defects in MCM substrate interconnections. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:260-265 [Conf]
  42. Vladimir A. Koval, Dmytro V. Fedasyuk
    The MCM's thermal testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:266-271 [Conf]
  43. A. J. van de Goor, G. N. Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik
    March LR: a test for realistic linked faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:272-280 [Conf]
  44. M. P. Kluth, François Simon, Jean-Yves Le Gall, E. Müller
    Design of a fault tolerant 100 Gbits solid-state mass memory for satellite. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:281-287 [Conf]
  45. Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz
    On minimizing the number of test points needed to achieve complete robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:288-295 [Conf]
  46. S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
    A new test pattern generation method for delay fault testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:296-301 [Conf]
  47. Valery A. Vardanian
    On completely robust path delay fault testable realization of logic functions. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:302-307 [Conf]
  48. S. Crepaux-Motte, Mireille Jacomino, Rene David
    An algebraic method for delay fault testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:308-315 [Conf]
  49. Mukund Sivaraman, Andrzej J. Strojwas
    A diagnosability metric for parametric path delay faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:316-323 [Conf]
  50. Peter Wohl, John A. Waicukauski, Matthew Graf
    Testing "untestable" faults in three-state circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:324-331 [Conf]
  51. Jonathan T.-Y. Chang, Edward J. McCluskey
    Quantitative analysis of very-low-voltage testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:332-337 [Conf]
  52. Michel Renovell, P. Huc, Yves Bertrand
    Bridging fault coverage improvement by power supply control. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:338-343 [Conf]
  53. Yuyun Liao, D. M. H. Walker
    Optimal voltage testing for physically-based faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:344-353 [Conf]
  54. Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham
    Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:354-361 [Conf]
  55. R. L. Campbell, P. Kuekes, David Y. Lepejian, W. Maly, Michael Nicolaidis, Alex Orailoglu
    Can Defect-Tolerant Chips Better Meet the Quality Challenge? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:362-363 [Conf]
  56. Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner
    Design Validation: Formal Verification vs. Simulation vs. Functional Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:364-365 [Conf]
  57. Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner
    BIST: Advantages or Limitations? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:366-367 [Conf]
  58. Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska
    Design and performance of CMOS TSPC cells for high speed pseudo random testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:368-373 [Conf]
  59. Dimitrios Kagaris, Spyros Tragoudas
    Generating deterministic unordered test patterns with counters. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:374-379 [Conf]
  60. Albrecht P. Stroele
    Test response compaction using arithmetic functions. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:380-386 [Conf]
  61. Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici
    Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:387-392 [Conf]
  62. Nur A. Touba, Edward J. McCluskey
    Applying two-pattern tests using scan-mapping. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:393-399 [Conf]
  63. Theo J. Powell
    Consistently dominant fault model for tristate buffer nets. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:400-404 [Conf]
  64. Jitendra Khare, Wojciech Maly, Nathan Tiday
    Fault characterization of standard cell libraries using inductive contamination. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:405-413 [Conf]
  65. Peter Dahlgren, Peter Lidén
    A fault model for switch-level simulation of gate-to-drain shorts. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:414-421 [Conf]
  66. Haluk Konuk, F. Joel Ferguson
    An unexpected factor in testing for CMOS opens: the die surface. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:422-429 [Conf]
  67. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
    On the effects of test compaction on defect coverage. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:430-437 [Conf]
  68. Minesh B. Amin, Bapiraju Vinnakota
    ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:438-443 [Conf]
  69. Anastasios Vergis, Carlos Tobon
    Testing trees for multiple faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:444-449 [Conf]
  70. Wei-Kang Huang, Fabrizio Lombardi
    An approach for testing programmable/configurable field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:450-455 [Conf]
  71. Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel
    Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:456-462 [Conf]
  72. Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya
    Isomorph-redundancy in sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:463-469 [Conf]
  73. Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham
    A novel test generation approach for parametric faults in linear analog circuits . [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:470-475 [Conf]
  74. Karim Arabi, Bozena Kaminska
    Oscillation-test strategy for analog and mixed-signal integrated circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:476-482 [Conf]
  75. Bapiraju Vinnakota
    Monitoring power dissipation for fault detection. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:483-488 [Conf]
  76. Chen-Yang Pan, Kwang-Ting Cheng
    Implicit functional testing for analog circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:489-494 [Conf]
  77. F. Mohamed, M. Manzouki, Anton Biasizzo, Franc Novak
    Analog circuit simulation and troubleshooting with FLAMES. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:495-501 [Conf]
  78. Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
    Delay Fault Testing: How Robust are Our Models? [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:502-503 [Conf]
  79. J. Braden, K. Brough, J. Evans, Martin P. McHugh, G. Young
    Board-Level BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:504-505 [Conf]
  80. J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
    Hardware-Software Co-Design for Test: It's the Last Straw! [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:506-507 [Conf]
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