Conferences in DBLP
K. De Test methodology for embedded cores which protects intellectual property. [Citation Graph (0, 0)][DBLP ] Conf ] Nur A. Touba , Bahram Pouya Testing Embedded Cores Using Partial Isolation Rings. [Citation Graph (0, 0)][DBLP ] Conf ] Kazumi Hatayama , Kazunori Hikone , T. Miyazaki , H. Yamada A practical approach to instruction-based test generation for functional modules of VLSI processors. [Citation Graph (0, 0)][DBLP ] Conf ] V. Kim , T. Chen Assessing SRAM test coverage for sub-micron CMOS technologies. [Citation Graph (0, 0)][DBLP ] Conf ] H. Goto , S. Nakamura , K. Iwasaki Experimental fault analysis of 1 Mb SRAM chips. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van de Goor , Issam B. S. Tlili Disturb Neighborhood Pattern Sensitive Fault. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele , Frank Mayer Methods to reduce test application time for accumulator-based self-test. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi , Donatella Sciuto Implicit test pattern generation constrained to cellular automata embedding. [Citation Graph (0, 0)][DBLP ] Conf ] Silvia Chiusano , Fulvio Corno , Paolo Prinetto , Matteo Sonza Reorda Cellular automata for deterministic sequential test pattern generation. [Citation Graph (0, 0)][DBLP ] Conf ] Rosa Rodríguez-Montañés , Joan Figueras Bridges in sequential CMOS circuits: current-voltage signatur. [Citation Graph (0, 0)][DBLP ] Conf ] Yiming Gong , Sreejit Chakravarty Using fault sampling to compute I/sub DDQ/ diagnostic test set. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Thibeault A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Chi Chen , Sandeep K. Gupta , Melvin A. Breuer High Quality Robust Tests for Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Christian Landrault , V. Moreda , Serge Pravossoudovitch An optimized BIST test pattern generator for delay testing. [Citation Graph (0, 0)][DBLP ] Conf ] Xiao-Tao Chen , Fred J. Meyer , Fabrizio Lombardi On the Fault Coverage of Interconnect Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Shing Chang , Sandeep K. Gupta , Melvin A. Breuer Analysis of Ground Bounce in Deep Sub-Micron Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Dahlgren Switch-level modeling of feedback faults using global oscillation control. [Citation Graph (0, 0)][DBLP ] Conf ] T. Haulin Built-in parametric test for controlled impedance I/Os. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski Using ATPG for clock rules checking in complex scan design. [Citation Graph (0, 0)][DBLP ] Conf ] Rathish Jayabharathi , Kyung Tek Lee , Jacob A. Abraham A Novel Solution for Chip-Level Functional Timing Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Kuang-Chien Chen , Kwang-Ting Cheng Incremental logic rectification. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Keim , Michael Martin , Bernd Becker , Rolf Drechsler , Paul Molitor Polynomial Formal Verification of Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Abdessatar Abderrahman , Eduard Cerny , Bozena Kaminska CLP-based Multifrequency Test Generation for Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi , Bozena Kaminska Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Zbigniew Jaworski , Mariusz Niewczas , Wieslaw Kuzmicz Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] N. J. Godambe , C.-J. Richard Shi Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS. [Citation Graph (0, 0)][DBLP ] Conf ] J. Borel , M. Cecchini , C. Malipeddi , Janusz Rajski , Yervant Zorian Systems On Silicon: Design and Test Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer , Bozena Kaminska , J. McDermid , V. Rayapathi , Donald L. Wheater Will 0.1um Digital Circuits Require Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Ismed Hartanto , Vamsi Boppana , Janak H. Patel , W. Kent Fuchs Diagnostic Test Pattern Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Khoche , Erik Brunvand Critical hazard free test generation for asynchronous circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Michele Favalli , Bruno Riccò Highly testable and compact single output comparator. [Citation Graph (0, 0)][DBLP ] Conf ] Xrysovalantis Kavousianos , Dimitris Nikolos Self-exercising self testing k-order comparators. [Citation Graph (0, 0)][DBLP ] Conf ] Valery A. Vardanian Exact probabilistic analysis of error detection for parity checkers. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Joan Figueras , Yervant Zorian Test of RAM-based FPGA: methodology and application to the interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Gizopoulos , Mihalis Psarakis , Antonis M. Paschalis Robust Sequential Fault Testing of Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] C. A. Fleischer , Lee A. Belfore II A new approach for testing artificial neural networks. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Dufaza , Hassan Ihs Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Pramodchandran N. Variyam , Abhijit Chatterjee , Naveena Nagi Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Soon Jyh Chang , Chung-Len Lee , Jwu E. Chen Functional test pattern generation for CMOS operational amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip Krishnaswamy , Elizabeth M. Rudnick , Janak H. Patel , Prithviraj Banerjee SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Laura Farinetti , Pier Luca Montessoro The Dynamic Rollback Problem in Concurrent Event-Driven Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jian-Kun Zhao , Elizabeth M. Rudnick , Janak H. Patel Static logic implication with application to redundancy identification. [Citation Graph (0, 0)][DBLP ] Conf ] Wim Verhaegen , Geert Van der Plas , Georges G. E. Gielen Automated test pattern generation for analog integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo J. Peralías , Adoración Rueda , José L. Huertas A DFT Technique for Analog-to-Digital Converters with digital correction. [Citation Graph (0, 0)][DBLP ] Conf ] W. D. Bartlett Determination of coherence errors in ADC spectral domain testing. [Citation Graph (0, 0)][DBLP ] Conf ] D. Cheung , Bernd Koenemann , S. Nishtala , B. West , D. Wu ATE for VLSI: What Challenges Lie Ahead? [Citation Graph (0, 0)][DBLP ] Conf ] J. Abraham , P. Frankl , Christian Landrault , Meryem Marzouki , Paolo Prinetto , Chantal Robach , Pascale Thévenod-Fosse Hardware Test: Can We Learn from Software Testing? [Citation Graph (0, 0)][DBLP ] Conf ] Priyank Kalla , Maciej J. Ciesielski Testability of Sequential Circuits with Multi-Cycle False Path. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On n-detection test sequences for synchronous sequential circuits343. [Citation Graph (0, 0)][DBLP ] Conf ] J. Yeandel , D. Thulborn , S. Jones An on-line testable UART implemented using IFIS. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Hlawiczka , Michael Gössel , Egor S. Sogomonyan A linear code-preserving signature analyzer COPMISR. [Citation Graph (0, 0)][DBLP ] Conf ] Giacomo Buonanno , M. Pugassi , Mariagiovanna Sami A high-level synthesis approach to design of fault-tolerant systems. [Citation Graph (0, 0)][DBLP ] Conf ] Samy Makar , Edward J. McCluskey ATPG for scan chain latches and flip-flops. [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Norwood , Edward J. McCluskey High-Level Synthesis for Orthogonal Sca. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Huan Chiang , Sandeep K. Gupta BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. [Citation Graph (0, 0)][DBLP ] Conf ] A. Jee , F. Joel Ferguson A methodolgy for characterizing cell testability. [Citation Graph (0, 0)][DBLP ] Conf ] V. Prepin , R. David Fault coverage of a long random test sequence estimated from a short simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir Random pattern testability of memory control logic. [Citation Graph (0, 0)][DBLP ] Conf ] Nur A. Touba Obtaining High Fault Coverage with Circular BIST Via State Skipping. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir Salvaging test windows in BIST diagnostic. [Citation Graph (0, 0)][DBLP ] Conf ] Can Ökmen , Martin Keim , Rolf Krieger , Bernd Becker On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Josep Altet , Antonio Rubio Differential Sensing Strategy for Dynamic Thermal Testing of ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Székely , Márta Rencz , Bernard Courtois Integrating on-chip temperature sensors into DfT schemes and BIST architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan T.-Y. Chang , Edward J. McCluskey SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal , Robert C. Aitken , J. Braden , Joan Figueras , S. Kumar , Hans-Joachim Wunderlich , Yervant Zorian Power Dissipation During Testing: Should We Worry About it? [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir , Jacob A. Abraham , H. Hao , C. Hunter , Wayne M. Needham , Ron G. Walther Microprocessor Test and Validation: Any New Avenues? [Citation Graph (0, 0)][DBLP ] Conf ] Phil Nigh , Wayne M. Needham , Kenneth M. Butler , Peter C. Maxwell , Robert C. Aitken An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. [Citation Graph (0, 0)][DBLP ] Conf ] 