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Conferences in DBLP

IEEE VLSI Test Symposium (vts)
1998 (conf/vts/1998)

  1. Stephen V. Kosonocky, Arthur A. Bright, Kevin Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Ben Parker, T. V. Rajeevakumar, Kevin Stawiasz
    Designing a Testable System on a Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:2-7 [Conf]
  2. Debashis Bhattacharya
    Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:8-14 [Conf]
  3. Mehrdad Nourani, Christos A. Papachristou
    Parallelism in Structural Fault Testing of Embedded Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:15-21 [Conf]
  4. Ovidio V. Maiuri, Will R. Moore
    Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:22-27 [Conf]
  5. Petra Nordholz, Dieter Treytnar, Jan Otterstedt, Hartmut Grabinski, Dirk Niggemeyer, T. W. Williams
    Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:28-33 [Conf]
  6. Kyung Tek Lee, Clay Nordquist, Jacob A. Abraham
    Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:34-41 [Conf]
  7. Jun Zhao, Fred J. Meyer, Fabrizio Lombardi
    Fault Detection and Diagnosis of Interconnects of Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:42-47 [Conf]
  8. Kazuki Shigeta, Toshio Ishiyama
    A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:48-53 [Conf]
  9. Pradip Bose
    Performance Test Case Generation for Microprocessors. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:54-61 [Conf]
  10. Masahiro Ishida, Dong Sam Ha, Takahiro J. Yamaguchi
    COMPACT: A Hybrid Method for Compressing Test Data. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:62-69 [Conf]
  11. Bahram Pouya, Nur A. Touba
    Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:70-77 [Conf]
  12. Albrecht P. Stroele
    Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:78-85 [Conf]
  13. Amitava Majumdar, Michio Komoda, Tim Ayres
    Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:86-91 [Conf]
  14. T. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos
    Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:92-97 [Conf]
  15. Kamran Zarrineh, Shambhu J. Upadhyaya, Philip Shephard III
    Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:98-105 [Conf]
  16. Víctor H. Champac, José Castillejos, Joan Figueras
    IDDQ Testing of Opens in CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:106-111 [Conf]
  17. Tsuyoshi Shinogi, Terumine Hayashi
    A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:112-117 [Conf]
  18. Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey
    Experimental Results for IDDQ and VLV Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:118-125 [Conf]
  19. Michael W. Tian, C.-J. Richard Shi
    Nonlinear Analog DC Fault Simulation by One-Step Relaxation. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:126-131 [Conf]
  20. Pramodchandran N. Variyam, Abhijit Chatterjee
    Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:132-137 [Conf]
  21. Madhu K. Iyer, Michael L. Bushnell
    Effect of Noise on Analog Circuit Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:138-144 [Conf]
  22. Heebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi
    Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:145-151 [Conf]
  23. Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:152-157 [Conf]
  24. Irith Pomeranz, Sudhakar M. Reddy
    On Synchronizing Sequences and Test Sequence Partitioning. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:158-167 [Conf]
  25. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    On Removing Redundant Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:168-175 [Conf]
  26. Hiroyuki Yotsuyanagi, Kozo Kinoshita
    Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:176-183 [Conf]
  27. Pinaki Mazumder
    Analysis of Failures in Deep Submicron SRAM Cells. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:184-187 [Conf]
  28. Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro
    Efficient Path Selection for Delay Testing Based on Partial Path Evaluation. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:188-193 [Conf]
  29. Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell
    On Delay-Untestable Paths and Stuck-Fault Redundancy. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:194-199 [Conf]
  30. Uwe Sparmann, Lars Köller
    Improving Path Delay Fault Testability by Path Removal. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:200-209 [Conf]
  31. Ganapathy Parthasarathy, Michael L. Bushnell
    Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:210-217 [Conf]
  32. Janusz Rajski, Jerzy Tyszer
    Design of Phase Shifters for BIST Applications. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:218-224 [Conf]
  33. Jacob Savir
    Distributed Generation of Weighted Random Patterns. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:225-233 [Conf]
  34. David Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz
    High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:234-238 [Conf]
  35. Iboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska, Fartoumi M. Hossein, Patrick Vincent
    Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:239-244 [Conf]
  36. Ralph Mason, Shing Ma
    Mixed Signal DFT at GHz Frequencies. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:245-253 [Conf]
  37. Dinos Moundanos, Jacob A. Abraham
    Using Verification Technology for Validation Coverage Analysis and Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:254-259 [Conf]
  38. Li-C. Wang, Magdy S. Abadir, Jing Zeng
    On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:260-265 [Conf]
  39. Rongchang Yan, Bruce C. Kim
    A Novel Routing Algorithm for MCM Substrate Verification Using Single-Ended Prob. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:266-273 [Conf]
  40. Douglas Williams, F. Joel Ferguson, Tracy Larrabee
    A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:274-282 [Conf]
  41. Fernando M. Gonçalves, João Paulo Teixeira
    Sampling Techniques of Non-Equally Probable Faults in VLSI System. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:283-288 [Conf]
  42. Irith Pomeranz, Sudhakar M. Reddy
    Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:289-295 [Conf]
  43. Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich
    Fast Self-Recovering Controllers. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:296-302 [Conf]
  44. Charles E. Stroud, Joe K. Tannehill Jr.
    Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:303-308 [Conf]
  45. Debaleena Das, Nur A. Touba
    Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:309-317 [Conf]
  46. José M. Miranda, Scott Davidson, Peter Dziel, Saman Adham, Steve Millman
    Test Reuse at System Level. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:318-319 [Conf]
  47. Jean-Michel Karam, Marcelo Lubaszewski, S. Blanton, A. Richardson
    Testing MEMS. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:320-321 [Conf]
  48. Sandip Gupta, Craig Gleason
    Validation and Test Problems for Cross Talk Noise. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:322-323 [Conf]
  49. Egor S. Sogomonyan, Adit D. Singh, Michael Gössel
    A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:324-331 [Conf]
  50. Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe
    Low Cost Partial Scan Design: A High Level Synthesis Approach. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:332-340 [Conf]
  51. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
    Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:341-347 [Conf]
  52. Xrysovalantis Kavousianos, Dimitris Nikolos
    Novel Single and Double Output TSC Berger Code Checkers. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:348-353 [Conf]
  53. Markus Seuring, Michael Gössel, Egor S. Sogomonyan
    A Structural Approach for Space Compaction for Concurrent Checking and BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:354-361 [Conf]
  54. Arsen Kuchukyan
    Estimation of Error Detection Probability and Latency of Checking Methods for a Given Circuit under Check. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:362-369 [Conf]
  55. Florence Azaïs, Michel Renovell, Yves Bertrand, J-C. Bodin
    Design-For-Testability for Switched-Current Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:370-375 [Conf]
  56. A. Lechner, A. Richardson, B. Hermes, Michael J. Ohletz
    A Design for Testability Study on a High Performance Automatic Gain Control Circuit. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:376-385 [Conf]
  57. R. de Vries, Augustus J. E. M. Janssen
    Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:386-393 [Conf]
  58. Sultan M. Al-Harbi, Sandeep K. Gupta
    A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:394-400 [Conf]
  59. A. J. van de Goor, Said Hamdioui
    Fault Models and Tests for Two-Port Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:401-410 [Conf]
  60. Piotr R. Sidorowicz, Janusz A. Brzozowski
    An Approach to Modeling and Testing Memories and Its Application to CAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:411-417 [Conf]
  61. Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
    Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:418-423 [Conf]
  62. Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda
    On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:424-429 [Conf]
  63. Bruce F. Cockburn, Albert L.-C. Kwong
    Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:430-439 [Conf]
  64. Dimitrios Karayiannis, Spyros Tragoudas
    A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:440-445 [Conf]
  65. Ilker Hamzaoglu, Janak H. Patel
    New Techniques for Deterministic Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:446-452 [Conf]
  66. Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Test Pattern Generation Methodology for Low-Power Consumption. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:453-459 [Conf]
  67. Peter C. Maxwell, Steve Baird, Wayne M. Needham, Al Crouch, Phil Nigh
    Best Methods for At-Speed Testing? [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:460-461 [Conf]
  68. Jeffrey S. Kasten
    An Introduction to RF Testing: Device, Method and System. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:462-469 [Conf]
  69. Keerthi Heragu
    Where We Might Stumble with Embedded-System Test. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:470- [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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