Conferences in DBLP
Nandu Tendolkar , Rajesh Raina , Rick Woltenberg , Xijiang Lin , Bruce Swanson , Greg Aldrich Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Amit R. Pandey , Janak H. Patel Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar , Richard A. Davies Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Eric MacDonald , Nur A. Touba Very Low Voltage Testing of SOI Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wanli Jiang , Erik Peterson Performance Comparison of VLV, ULV, and ECR Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Wen Tseng , James Li , Edward J. McCluskey Experimental Results for Slow-Speed Testing. [Citation Graph (0, 0)][DBLP ] Conf ] J. Borel , Anand Raghunathan , Jim Sproch , Michael Howells , Janusz Rajski Innovations in Test Automation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gössel , Egor S. Sogomonyan , Adit D. Singh Scan-Path with Directly Duplicated and Inverted Duplicated Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Aiman El-Maleh , Ali Al-Suwaiyan An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi Logic BIST and Scan Test Techniques for Multiple Identical Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Madge , Manu Rehani , Kevin Cota , W. Robert Daasch Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas S. Barnett , Adit D. Singh , Matt Grady , Kathleen G. Purdy Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Sagar S. Sabade , D. M. H. Walker Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Lee Song , Rudy Garcia , Andrew Levy , Donald L. Wheater A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required? [Citation Graph (0, 0)][DBLP ] Conf ] Anshuman Chandra , Krishnendu Chakrabarty , Rafael A. Medina How Effective are Compression Codes for Reducing Test Data Volume? [Citation Graph (0, 0)][DBLP ] Conf ] Ajay Khoche , Erik H. Volkerink , Jochen Rivoir , Subhasish Mitra Test Vector Compression Using EDA-ATE Synergies. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhakar M. Reddy , Kohei Miyase , Seiji Kajihara , Irith Pomeranz On Test Data Volume Reduction for Multiple Scan Chain Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ganapathy Kasturirangan , Michael S. Hsiao Spectrum-Based BIST in Complex SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-kai Chen , Chih-Hu Wang , Chau-chin Su A Self Calibrated ADC BIST Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Chee-Kian Ong , Kwang-Ting (Tim) Cheng Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Bottoms , Lee Song , Paul Patton , Wilhelm Radermacher A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution? [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Nourani , James Chin Testing High-Speed SoCs Using Low-Speed ATEs. [Citation Graph (0, 0)][DBLP ] Conf ] Madhu K. Iyer , Kwang-Ting Cheng Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] René David , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel On Using Efficient Test Sequences for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Ranganathan Sankaralingam , Nur A. Touba Controlling Peak Power During Scan Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Koji Ishida , Kohei Miyase Test Vector Modification for Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Ismet Bayraktaroglu , Alex Orailoglu Test Power Reduction through Minimization of Scan Chain Transitions. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken , Mustapha Slamani , H. Ding , William R. Eisenstadt , Sanghoon Choi , John McLaughlin Wireless Test. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Osseiran , William De Wilkins , Barry Baril , Sassan Tabatabaei , Fidel Muradali , Ken Posse , Lee Song Analog and Mixed Signal BIST: Too Much, Too Little, Too Late? [Citation Graph (0, 0)][DBLP ] Conf ] Julie Segal , Rene Segers , Rob Aitken , S. Eichenberge , A. Gattike , M. Millegen , R. Seger , S. Venkataraman Test as a Key Enabler for Faster Yield Ramp-Up. [Citation Graph (0, 0)][DBLP ] Conf ] Enamul Amyeen , Irith Pomeranz , W. Kent Fuchs Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Mo James Li , Edward J. McCluskey Diagnosis of Sequence-Dependent Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] José Vicente Calvano , Vladimir Castro Alves , Antônio C. Mesquita , Marcelo Lubaszewski Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro J. Yamaguchi , Masahiro Ishida , Mani Soma , Louis Malarsie , Hirobumi Musha Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. [Citation Graph (0, 0)][DBLP ] Conf ] Sule Ozev , Alex Orailoglu Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Nektarios Kranitis , Antonis M. Paschalis , Dimitris Gizopoulos , Yervant Zorian Instruction-Based Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Berrojo , Isabel González , Fulvio Corno , Matteo Sonza Reorda , Giovanni Squillero , Luis Entrena , Celia López An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Vivekananda M. Vedula , Jacob A. Abraham , Jayanta Bhadra Program Slicing for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , Edward J. McCluskey , Samy Makar Design for Testability and Testing of IEEE 1149.1 Tap Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Iyengar , Krishnendu Chakrabarty , Erik Jan Marinissen On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Kumar Goel , Erik Jan Marinissen Cluster-Based Test Architecture Design for System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi , Klaus-Dieter Hilliges , David C. Keezer , Sassan Tabatabaei Multi-GigaHertz Testing Challenges and Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Kumar N. Dwarakanath , R. D. (Shawn) Blanton Exploiting Dominance and Equivalence using Fault Tuples. [Citation Graph (0, 0)][DBLP ] Conf ] Narayanan Krishnamurthy , Jayanta Bhadra , Magdy S. Abadir , Jacob A. Abraham Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? [Citation Graph (0, 0)][DBLP ] Conf ] Kuo-Liang Cheng , Jen-Chieh Yeh , Chih-Wea Wang , Chih-Tsun Huang , Cheng-Wen Wu RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. [Citation Graph (0, 0)][DBLP ] Conf ] Yukio Okuda Eigen-Signatures for Regularity-based IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Thibeault Speeding-Up IDDQ Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Bhunia , Kaushik Roy Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. McCluskey , Subhasish Mitra , Bob Madge , Peter C. Maxwell , Phil Nigh , Mike Rodgers Debating the Future of Burn-In. [Citation Graph (0, 0)][DBLP ] Conf ] B. Courtoi , M. Forshaw Beyond CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] G. Roberts Challenges of Mixed-Signal Board Design and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Satoshi Ohtake , Hideo Fujiwara , Shunjiro Miwa A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Hosokawa , Hiroshi Date , Michiaki Muraoka A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Attarha , Mehrdad Nourani Test Pattern Generation for Signal Integrity Faults on Long Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Rodger Schuttert , Frans de Jong , Ben Kup Improved Test Monitor Circuit in Power Pin DfT. [Citation Graph (0, 0)][DBLP ] Conf ] Achintya Halder , Abhijit Chatterjee , Pramodchandran N. Variyam , John Ridley Measuring Stray Capacitance on Tester Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Abhishek Singh , Jim Plusquellic , Anne E. Gattiker Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Kambiz Komeyli , Eric W. Savage , Michael J. Carruthers , Bret T. Stastny , Sujit T. Zachariah Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Ankur Jain Fault Models for Speed Failures Caused by Bridges and Opens. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Kundu , R. D. (Shawn) Blanton Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Fu Li , Ruey-Shing Tzeng , Cheng-Wen Wu Testing and Diagnosing Embedded Content Addressable Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , Zaid Al-Ars , A. J. van de Goor Testing Static and Dynamic Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , A. J. van de Goor Approximating Infinite Dynamic Behavior for DRAM Cell Defects. [Citation Graph (0, 0)][DBLP ] Conf ] C.-H. Chia , Sujit Dey , Faraydon Karim , Haluk Konuk , Keesup Kim Validation and Test of Network Processors and ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Erik H. Volkerink , Ajay Khoche , Jochen Rivoir , Klaus D. Hilliges Test Economics for Multi-site Test with Modern Cost Reduction Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Sekar , Sujit Dey LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Theo Gonciari , Bashir M. Al-Hashimi , Nicola Nicolici Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Diego Vázquez , Gloria Huertas , Gildas Leger , Adoración Rueda , José L. Huertas Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Vincent Beroulle , Yves Bertrand , Laurent Latorre , Pascal Nouet Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Fidel Muradali , Mike Ricchetti , Bart Vermeulen , Bulent I. Dervisoglu , Bob Gottlieb , Bernd Koenemann , C. J. Clark Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? [Citation Graph (0, 0)][DBLP ] Conf ] Jaume Segura , Vivek De , Ali Keshavarzi Challenges in Nanometric Technology Scaling: Trends and Projections. [Citation Graph (0, 0)][DBLP ] Conf ] Salvador Mir , H. Bederr , R. D. (Shawn) Blanton , Hans G. Kerkhoff , H. J. Klim SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? [Citation Graph (0, 0)][DBLP ] Conf ] 