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Conferences in DBLP

IEEE VLSI Test Symposium (vts)
2002 (conf/vts/2002)

  1. Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich
    Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:3-8 [Conf]
  2. Amit R. Pandey, Janak H. Patel
    Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:9-15 [Conf]
  3. Dilip K. Bhavsar, Richard A. Davies
    Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:16-24 [Conf]
  4. Eric MacDonald, Nur A. Touba
    Very Low Voltage Testing of SOI Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:25-30 [Conf]
  5. Wanli Jiang, Erik Peterson
    Performance Comparison of VLV, ULV, and ECR Tests. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:31-36 [Conf]
  6. Chao-Wen Tseng, James Li, Edward J. McCluskey
    Experimental Results for Slow-Speed Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:37-42 [Conf]
  7. J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski
    Innovations in Test Automation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:43-46 [Conf]
  8. Michael Gössel, Egor S. Sogomonyan, Adit D. Singh
    Scan-Path with Directly Duplicated and Inverted Duplicated Registers. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:47-52 [Conf]
  9. Aiman El-Maleh, Ali Al-Suwaiyan
    An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:53-59 [Conf]
  10. Karim Arabi
    Logic BIST and Scan Test Techniques for Multiple Identical Blocks. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:60-68 [Conf]
  11. Robert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch
    Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:69-74 [Conf]
  12. Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy
    Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:75-80 [Conf]
  13. Sagar S. Sabade, D. M. H. Walker
    Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:81-86 [Conf]
  14. Lee Song, Rudy Garcia, Andrew Levy, Donald L. Wheater
    A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:87-90 [Conf]
  15. Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina
    How Effective are Compression Codes for Reducing Test Data Volume? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:91-96 [Conf]
  16. Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra
    Test Vector Compression Using EDA-ATE Synergies. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:97-102 [Conf]
  17. Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
    On Test Data Volume Reduction for Multiple Scan Chain Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:103-110 [Conf]
  18. Ganapathy Kasturirangan, Michael S. Hsiao
    Spectrum-Based BIST in Complex SOCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:111-116 [Conf]
  19. Hung-kai Chen, Chih-Hu Wang, Chau-chin Su
    A Self Calibrated ADC BIST Methodology. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:117-122 [Conf]
  20. Chee-Kian Ong, Kwang-Ting (Tim) Cheng
    Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:123-128 [Conf]
  21. Bill Bottoms, Lee Song, Paul Patton, Wilhelm Radermacher
    A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:129-132 [Conf]
  22. Mehrdad Nourani, James Chin
    Testing High-Speed SoCs Using Low-Speed ATEs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:133-138 [Conf]
  23. Madhu K. Iyer, Kwang-Ting Cheng
    Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:139-144 [Conf]
  24. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    On Using Efficient Test Sequences for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:145-152 [Conf]
  25. Ranganathan Sankaralingam, Nur A. Touba
    Controlling Peak Power During Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:153-159 [Conf]
  26. Seiji Kajihara, Koji Ishida, Kohei Miyase
    Test Vector Modification for Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:160-165 [Conf]
  27. Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
    Test Power Reduction through Minimization of Scan Chain Transitions. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:166-172 [Conf]
  28. Robert C. Aitken, Mustapha Slamani, H. Ding, William R. Eisenstadt, Sanghoon Choi, John McLaughlin
    Wireless Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:173-174 [Conf]
  29. Adam Osseiran, William De Wilkins, Barry Baril, Sassan Tabatabaei, Fidel Muradali, Ken Posse, Lee Song
    Analog and Mixed Signal BIST: Too Much, Too Little, Too Late? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:175-176 [Conf]
  30. Julie Segal, Rene Segers, Rob Aitken, S. Eichenberge, A. Gattike, M. Millegen, R. Seger, S. Venkataraman
    Test as a Key Enabler for Faster Yield Ramp-Up. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:177-180 [Conf]
  31. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs
    Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:181-186 [Conf]
  32. Chien-Mo James Li, Edward J. McCluskey
    Diagnosis of Sequence-Dependent Chips. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:187-192 [Conf]
  33. Shi-Yu Huang
    Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:193-200 [Conf]
  34. José Vicente Calvano, Vladimir Castro Alves, Antônio C. Mesquita, Marcelo Lubaszewski
    Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:201-206 [Conf]
  35. Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie, Hirobumi Musha
    Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:207-212 [Conf]
  36. Sule Ozev, Alex Orailoglu
    Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:213-222 [Conf]
  37. Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
    Instruction-Based Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:223-228 [Conf]
  38. Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
    An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:229-236 [Conf]
  39. Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra
    Program Slicing for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:237-246 [Conf]
  40. Subhasish Mitra, Edward J. McCluskey, Samy Makar
    Design for Testability and Testing of IEEE 1149.1 Tap Controller. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:247-252 [Conf]
  41. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:253-258 [Conf]
  42. Sandeep Kumar Goel, Erik Jan Marinissen
    Cluster-Based Test Architecture Design for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:259-264 [Conf]
  43. Karim Arabi, Klaus-Dieter Hilliges, David C. Keezer, Sassan Tabatabaei
    Multi-GigaHertz Testing Challenges and Solutions. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:265-268 [Conf]
  44. Kumar N. Dwarakanath, R. D. (Shawn) Blanton
    Exploiting Dominance and Equivalence using Fault Tuples. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:269-274 [Conf]
  45. Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
    Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:275-280 [Conf]
  46. Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
    RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:281-288 [Conf]
  47. Yukio Okuda
    Eigen-Signatures for Regularity-based IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:289-294 [Conf]
  48. Claude Thibeault
    Speeding-Up IDDQ Measurements. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:295-301 [Conf]
  49. Swarup Bhunia, Kaushik Roy
    Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:302-310 [Conf]
  50. Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers
    Debating the Future of Burn-In. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:311-314 [Conf]
  51. B. Courtoi, M. Forshaw
    Beyond CMOS. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:315-316 [Conf]
  52. G. Roberts
    Challenges of Mixed-Signal Board Design and Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:317-320 [Conf]
  53. Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa
    A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:321-327 [Conf]
  54. Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
    A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:328-335 [Conf]
  55. Amir Attarha, Mehrdad Nourani
    Test Pattern Generation for Signal Integrity Faults on Long Interconnects. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:336-344 [Conf]
  56. Rodger Schuttert, Frans de Jong, Ben Kup
    Improved Test Monitor Circuit in Power Pin DfT. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:345-350 [Conf]
  57. Achintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley
    Measuring Stray Capacitance on Tester Hardware. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:351-356 [Conf]
  58. Abhishek Singh, Jim Plusquellic, Anne E. Gattiker
    Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:357-366 [Conf]
  59. Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah
    Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:367-372 [Conf]
  60. Sreejit Chakravarty, Ankur Jain
    Fault Models for Speed Failures Caused by Bridges and Opens. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:373-378 [Conf]
  61. Rahul Kundu, R. D. (Shawn) Blanton
    Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:379-388 [Conf]
  62. Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu
    Testing and Diagnosing Embedded Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:389-394 [Conf]
  63. Said Hamdioui, Zaid Al-Ars, A. J. van de Goor
    Testing Static and Dynamic Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:395-400 [Conf]
  64. Zaid Al-Ars, A. J. van de Goor
    Approximating Infinite Dynamic Behavior for DRAM Cell Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:401-406 [Conf]
  65. C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim
    Validation and Test of Network Processors and ASICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:407-410 [Conf]
  66. Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus D. Hilliges
    Test Economics for Multi-site Test with Modern Cost Reduction Techniques. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:411-416 [Conf]
  67. Krishna Sekar, Sujit Dey
    LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:417-422 [Conf]
  68. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:423-432 [Conf]
  69. Diego Vázquez, Gloria Huertas, Gildas Leger, Adoración Rueda, José L. Huertas
    Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:433-438 [Conf]
  70. Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
    Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:439-444 [Conf]
  71. Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark
    Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:445-446 [Conf]
  72. Jaume Segura, Vivek De, Ali Keshavarzi
    Challenges in Nanometric Technology Scaling: Trends and Projections. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:447-448 [Conf]
  73. Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim
    SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:449-450 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002