Conferences in DBLP
Vinod K. Agarwal VTS 1999 Keynote Address Embedded Test OR External Test. [Citation Graph (0, 0)][DBLP ] Conf ] Hugo De Man Design Technology Research and Education for Deep-Submicron Systems of the Next Century. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Kwang-Ting (Tim) Cheng , Srimat T. Chakradhar Testing High Speed VLSI Devices Using Slower Testers. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnendu Chakrabarty , Brian T. Murray , Vikram Iyengar Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. [Citation Graph (0, 0)][DBLP ] Conf ] R. Dean Adams , Edmond S. Cooley The Limits of Digital Testing for Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Batcher , Christos A. Papachristou Instruction Randomization Self Test For Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Yervant Zorian Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gössel , A. A. Morosov , Egor S. Sogomonyan A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas G. Veneris , Ibrahim N. Hajj , Srikanth Venkataraman , W. Kent Fuchs Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Takahashi , Kwame Osei Boateng , Yuzo Takamatsu A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Nayak , D. M. H. Walker Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Margolese , F. Joel Ferguson Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Shing Chang , Sandeep K. Gupta , Melvin A. Breuer Test Generation for Ground Bounce in Internal Logic Circuitry. [Citation Graph (0, 0)][DBLP ] Conf ] Josef Schmid , Joachim Knäblein Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Jas , Jayabrata Ghosh-Dastidar , Nur A. Touba Scan Vector Compression/Decompression Using Statistical Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Sameer Sharma , Michael S. Hsiao Partial Scan Using Multi-Hop State Reachability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Aitken Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Th. Calin , Lorena Anghel , Michael Nicolaidis Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Thibeault On the Comparison of IDDQ and IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy A Flexible Path Selection Procedure for Path Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Hyungwon Kim , John P. Hayes Delay Fault Testing of Designs with Embedded IP Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Jayabrata Ghosh-Dastidar , Nur A. Touba Adaptive Techniques for Improving Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip A. Thaker , Vishwani D. Agrawal , Mona E. Zaghloul Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Shen , Jacob A. Abraham Verification of Processor Microarchitectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Vinodh Gopal Techniques to Encode and Compress Fault Dictionaries. [Citation Graph (0, 0)][DBLP ] Conf ] Enamul Amyeen , W. Kent Fuchs , Irith Pomeranz , Vamsi Boppana Implication and Evaluation Techniques for Proving Fault Equivalence. [Citation Graph (0, 0)][DBLP ] Conf ] Pramodchandran N. Variyam , Junwei Hou , Abhijit Chatterjee Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jiun-Lang Huang , Chen-Yang Pan , Kwang-Ting Cheng Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Sunter , Naveena Nagi Test Metrics for Analog Parametric Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Grzegorz Mrugalski , Jerzy Tyszer Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Ben Jone , Der-Cheng Huang , S. C. Wu , K. J. Lee An Efficient BIST Method for Small Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Mihalis Psarakis , Antonis M. Paschalis , Dimitris Gizopoulos , Yervant Zorian An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Ruifeng Guo , Irith Pomeranz , Sudhakar M. Reddy A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael R. Grimaila , Sooryong Lee , Jennifer Dworak , Kenneth M. Butler , Bret Stewart , Hari Balachandran , Bryan Houchins , Vineet Mathur , Jaehong Park , Li-C. Wang , M. Ray Mercer REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhakar M. Reddy , Irith Pomeranz , Nadir Z. Basturkmen , Xijiang Lin Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce C. Kim , Krishna Marella A Novel Test Methodology for MEMS Magnetic Micromotors. [Citation Graph (0, 0)][DBLP ] Conf ] Zao Yang , K.-T. Cheng , K. L. Tai A New Bare Die Test Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Ramakrishna Voorakaranam , Abhijit Chatterjee Hierarchical Test Generation for Analog Circuits Using Incremental Test Development. [Citation Graph (0, 0)][DBLP ] Conf ] Iyad Rayane , J. Velasco-Medina , Michael Nicolaidis A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sassan Tabatabaei , André Ivanov A Current Integrator for BIST of Mixed-Signal ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Jinyan Zhang , Sam D. Huynh , Mani Soma A Test Point Insertion Algorithm for Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelino B. Santos , F. M. Gongalves , Isabel C. Teixeira , João Paulo Teixeira Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald J. Hayne , Barry W. Johnson Behavioral Fault Modeling in a VHDL Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Silvia Chiusano , Fulvio Corno , Paolo Prinetto RT-level TPG Exploiting High-Level Synthesis Information. [Citation Graph (0, 0)][DBLP ] Conf ] Xrysovalantis Kavousianos , Dimitris Nikolos Modular TSC Checkers for Bose-Lin and Bose Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele , Steffen Tarnick Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code. [Citation Graph (0, 0)][DBLP ] Conf ] Debaleena Das , Nur A. Touba Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Zhao , Fred J. Meyer , Fabrizio Lombardi Maximal Diagnosis of Interconnects of Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Sybille Hellebrand , Hans-Joachim Wunderlich , Alexander A. Ivaniuk , Yuri V. Klimets , Vyacheslav N. Yarmolik Error Detecting Refreshment for Embedded DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Kamran Zarrineh , Shambhu J. Upadhyaya A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units. [Citation Graph (0, 0)][DBLP ] Conf ] Srivaths Ravi , Ganesh Lakshminarayana , Niraj K. Jha TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch A Test Vector Inhibiting Technique for Low Energy BIST Design. [Citation Graph (0, 0)][DBLP ] Conf ] Carter Hamilton , Gretchen Gibson , Sajitha Wijesuriya , Charles E. Stroud Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access. [Citation Graph (0, 0)][DBLP ] Conf ] E. Isern , M. Roca , J. Segura Analyzing the Need for ATPG Targeting GOS Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Ankur Jain , Michael S. Hsiao , Vamsi Boppana , Masahiro Fujita On the Evaluation of Arbitrary Defect Coverage of Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Wanli Jiang , Bapiraju Vinnakota Defect-Oriented Test Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Philip P. Shirvani , Edward J. McCluskey PADded Cache: A New Fault-Tolerance Technique for Cache Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Ismet Bayraktaroglu , Alex Orailoglu Low-Cost On-Line Test for Digital Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Rebaudengo , Matteo Sonza Reorda Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM . [Citation Graph (0, 0)][DBLP ] Conf ] Jingjing Xu , Rahul Kundu , F. Joel Ferguson A Systematic DFT Procedure for Library Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Bhattacharya Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo R. Alves , J. M. Martins Ferreira From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1. [Citation Graph (0, 0)][DBLP ] Conf ] 