Conferences in DBLP
Foreword. [Citation Graph (0, 0)][DBLP ] Conf ] Organizing Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Steering Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Program Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Acknowledgments. [Citation Graph (0, 0)][DBLP ] Conf ] Test Technology Technical Council. [Citation Graph (0, 0)][DBLP ] Conf ] Test Technology Educational Program: Overview of Tutorials. [Citation Graph (0, 0)][DBLP ] Conf ] VTS 2004 Best Paper Award. [Citation Graph (0, 0)][DBLP ] Conf ] VTS 2004 Best Panel Award. [Citation Graph (0, 0)][DBLP ] Conf ] VTS 2004 Best Innovative Practices Session Award. [Citation Graph (0, 0)][DBLP ] Conf ] Reviewers. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip K. Bhavsar A Built-in Self-Test Method for Write-only Content Addressable Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Jen-Chieh Yeh , Yan-Ting Lai , Yuan-Yuan Shih , Cheng-Wen Wu , Chien-Hung Ho , Yen-Tai Lin Flash Memory Built-In Self-Diagnosis with Test Mode Control. [Citation Graph (0, 0)][DBLP ] Conf ] Ismet Bayraktaroglu , Olivier Caty , Yickkei Wong Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Shing Chang , Sreejit Chakravarty , Hiep Hoang , Nick Thorpe , Khen Wee Transition Tests for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Leonard Lee , Li-C. Wang , Praveen Parvathala , T. M. Mak On Silicon-Based Speed Path Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Nisar Ahmed , C. P. Ravikumar , Mohammad Tehranipoor , Jim Plusquellic At-Speed Transition Fault Testing With Low Speed Scan Enable. [Citation Graph (0, 0)][DBLP ] Conf ] Gurgen Harutunyan , Valery A. Vardanian , Yervant Zorian Minimal March Tests for Unlinked Static Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Fu Li , Chou-Kun Lin Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Baosheng Wang , Yuejian Wu , Josh Yang , André Ivanov , Yervant Zorian SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Darren Aaberge , Ken Mockler , Dieu Van Dinh , Raoul Belleau , Tim Donovan , Reid Hewlitt Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Hitoshi Iwai , Atsushi Nakayama , Naoko Itoga , Kotaro Omata Cantilever Type Probe Card for At-Speed Memory Test on Wafer. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Omaña , Daniele Rossi , Cecilia Metra Low Cost Scheme for On-Line Clock Skew Compensation. [Citation Graph (0, 0)][DBLP ] Conf ] Abdul Wahid Hakmi , Hans-Joachim Wunderlich , Valentin Gherman , Michael Garbers , Jürgen Schlöffel Implementing a Scheme for External Deterministic Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Charles H.-P. Wen , Li-C. Wang , Kwang-Ting Cheng , Kai Yang , Wei-Ting Liu , Ji-Jan Chen On A Software-Based Self-Test Methodology and Its Application. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Jerzy Tyszer Synthesis of X-Tolerant Convolutional Compactors. [Citation Graph (0, 0)][DBLP ] Conf ] Dongwoo Hong , Cameron Dryden , Gordon Saksena An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Anup P. Jose , Keith A. Jenkins , Scott K. Reynolds On-Chip Spectrum Analyzer for Analog Built-In Self Test. [Citation Graph (0, 0)][DBLP ] Conf ] Soumendu Bhattacharya , Abhijit Chatterjee Production Test Methods for Measuring 'Out-of-Band' Interference of Ultra Wide Band (UWB) Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Davidson Towards an Understanding of No Trouble Found Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin N. Lee , Li-C. Wang , Magdy S. Abadir Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Intaik Park , Ahmad A. Al-Yamani , Edward J. McCluskey Effective TARO Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Azimane , Ananta K. Majhi , Guido Gronthoud , Maurice Lousberg A New Algorithm for Dynamic Faults Detection in RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian Hage-Hassan Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. [Citation Graph (0, 0)][DBLP ] Conf ] John C. Koob , Sue Ann Ung , Ashwin S. Rao , Daniel A. Leder , Craig S. Joly , Kristopher C. Breen , Tyler L. Brandon , Michael Hume , Bruce F. Cockburn , Duncan G. Elliott Test and Characterization of a Variable-Capacity Multilevel DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Chieh Wang , Jing-Jia Liou , Yen-Lin Peng , Chih-Tsun Huang , Cheng-Wen Wu A BIST Scheme for FPGA Interconnect Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Ghazanfar Asadi , Mehdi Baradaran Tahoori Soft Error Mitigation for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] N. Dumas , Florence Azaïs , Laurent Latorre , Pascal Nouet On-Chip Electro-Thermal Stimulus Generation for a MEMS-Based Magnetic Field Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Beck , Olivier Barondeau , Frank Poehl , Xijiang Lin , Ron Press Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Chieh Lin , Feng Lu , Kwang-Ting Cheng Pseudo-Functional Scan-based BIST for Delay Fault. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Wang , Xiang Lu , Wangqi Qiu , Ziding Yue , Steve Fancler , Weiping Shi , D. M. H. Walker Static Compaction of Delay Tests Considering Power Supply Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Selim Sermet Akbay , Abhijit Chatterjee Built-In Test of RF Components Using Mapped Feature Extraction Sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Valdes-Garcia , Radhika Venkatasubramanian , Rangakrishnan Srinivasan , José Silva-Martínez , Edgar Sánchez-Sinencio A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers. [Citation Graph (0, 0)][DBLP ] Conf ] Achintya Halder , Abhijit Chatterjee Low-Cost Alternate EVM Test for Wireless Receiver Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Yoshiyuki Yamashita , Seiji Kajihara , Laung-Terng Wang , Kewal K. Saluja , Kozo Kinoshita On Low-Capture-Power Test Generation for Scan Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Kirti Joshi , Eric MacDonald Reduction of Instantaneous Power by Ripple Scan Clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Min-Hao Chiu , Chien-Mo James Li Jump Scan: A DFT Technique for Low Power Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Cameron Dryden Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Qikai Chen , Hamid Mahmoodi-Meimand , Swarup Bhunia , Kaushik Roy Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Abdulkadir Utku Diril , Yuvraj Singh Dhillon , Abhijit Chatterjee , Adit D. Singh Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Shalini Ghosh , Sugato Basu , Nur A. Touba Synthesis of Low Power CED Circuits Based on Parity Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Su , Krishnendu Chakrabarty Defect Tolerance for Gracefully-Degradable Microfluidics-Based Biochips. [Citation Graph (0, 0)][DBLP ] Conf ] Kartik Mohanram Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Yi-Shing Chang , Hiep Hoang , Sridhar Jayaraman , Silvio Picano , Cheryl Prunty , Eric W. Savage , Rehan Sheikh , Eric N. Tran , Khen Wee Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Ilia Polian , Sandip Kundu , Jean Marc Galliere , Piet Engelke , Michel Renovell , Bernd Becker Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Chunsheng Liu , Vikram Iyengar , Jiangfan Shi , Érika F. Cota Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski , Sanjay Patel , Cy Hay , Emil Gizdarski , Ben Mathew Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Rao Desineni , R. D. (Shawn) Blanton Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Erkan Acar , Sule Ozev Diagnosis of Failing Component in RF Receivers through Adaptive Full-Path Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Yun-Che Wen A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo Pereira , Antonio Andrade Jr. , Tiago R. Balen , Marcelo Lubaszewski , Florence Azaïs , Michel Renovell Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris Constructive Derivation of Analog Specification Test Criteria. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad A. Al-Yamani , Erik Chmelar , Mikhail Grinchuck Segmented Addressable Scan Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Ting Lin , Tony Ambler An Economic Selecting Model for DFT Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Loganathan Lingappan , Niraj K. Jha Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ritesh P. Turakhia , Brady Benware , Robert Madge , Thaddeus T. Shannon , W. Robert Daasch Defect Screening Using Independent Component Analysis on I_DDQ. [Citation Graph (0, 0)][DBLP ] Conf ] Dhruva Acharyya , Jim Plusquellic Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Nourani , Mohammad Tehranipoor , Nisar Ahmed Pattern Generation and Estimation for Power Supply Noise Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] 