The SCEAS System
Navigation Menu

Conferences in DBLP

IEEE VLSI Test Symposium (vts)
2004 (conf/vts/2004)

  1. Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer
    Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:9-15 [Conf]
  2. Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, Francois-Fabien Ferhani, Edward Li, Subhasish Mitra
    ELF-Murphy Data on Defects and Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:16-22 [Conf]
  3. Srikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo
    An Experimental Study of N-Detect Scan ATPG Patterns on a Processor. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:23-30 [Conf]
  4. Manish Sharma, Janak H. Patel
    What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:31-36 [Conf]
  5. Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
    A Statistical Fault Coverage Metric for Realistic Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:37-42 [Conf]
  6. Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger
    Delay Defect Screening using Process Monitor Structures. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:43-52 [Conf]
  7. Josep Rius Vázquez, José Pineda de Gyvez
    Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:53-58 [Conf]
  8. Claude Thibeault
    On New Current Signatures and Adaptive Test Technique Combination. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:59-64 [Conf]
  9. Sagar S. Sabade, D. M. H. Walker
    On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:65-72 [Conf]
  10. Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams
    Changing the Scan Enable during Shift. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:73-78 [Conf]
  11. C. V. Krishna, Nur A. Touba
    3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:79-86 [Conf]
  12. Michael R. Nelms, Kevin Gorman, Darren Anand
    Generating At-Speed Array Fail Maps with Low-Speed ATE. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:87-96 [Conf]
  13. Debashis Nayak, Srikanth Venkataraman, Paul J. Thadikaran
    Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:97-102 [Conf]
  14. Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre
    Yield Analysis of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:103-108 [Conf]
  15. Erik Chmelar, Shahin Toutounchi
    FPGA Bridging Fault Detection and Location via Differential I{DDQ}. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:109-116 [Conf]
  16. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:117-122 [Conf]
  17. Mohamed Azimane, Ananta K. Majhi
    New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:123-128 [Conf]
  18. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
    March iC-: An Improved Version of March C- for ADOFs Detection. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:129-138 [Conf]
  19. Nilmoni Deb, R. D. (Shawn) Blanton
    Multi-Modal Built-In Self-Test for Symmetric Microsystems. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:139-147 [Conf]
  20. Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
    A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:148-153 [Conf]
  21. Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure
    A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:154-170 [Conf]
  22. Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
    The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:171-178 [Conf]
  23. Josep Altet, Antonio Rubio, M. Amine Salhi, J. L. Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov
    Sensing temperature in CMOS circuits for Thermal Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:179-184 [Conf]
  24. Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware
    Detection of Temperature Sensitive Defects Using ZTC. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:185-192 [Conf]
  25. Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
    Planar High Performance Ring Generators. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:193-198 [Conf]
  26. Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel
    Logic BIST Using Constrained Scan Cells. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:199-205 [Conf]
  27. Salvador Manich, L. García, L. Balado, E. Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
    BIST Technique by Equally Spaced Test Vector Sequences. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:206-216 [Conf]
  28. Sule Ozev, Christian Olgaard
    Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:217-222 [Conf]
  29. Qi Wang, Yi Tang, Mani Soma
    GHz RF Front-end Bandwidth Time Domain Measurement. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:223-228 [Conf]
  30. Soumendu Bhattacharya, Ganesh Srinivasan, Sasikumar Cherubal, Achintya Halder, Abhijit Chatterjee
    System-level Testing of RF Transmitter Specifications Using Optimized Periodic Bitstreams. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:229-236 [Conf]
  31. Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian
    Reducing Embedded SRAM Test Time under Redundancy Constraints. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:237-242 [Conf]
  32. Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk
    Memory BIST Using ESP. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:243-248 [Conf]
  33. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
    A Methodology for Design and Evaluation of Redundancy Allocation Algorithms. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:249-260 [Conf]
  34. Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
    An On-Chip Transfer Function Characterization System for Analog Built-in Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:261-266 [Conf]
  35. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    A Scalable On-Chip Jitter Extraction Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:267-272 [Conf]
  36. Selim Sermet Akbay, Abhijit Chatterjee
    Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:273-290 [Conf]
  37. Mehdi Baradaran Tahoori, Mariam Momenzadeh, Jing Huang, Fabrizio Lombardi
    Defects and Faults in Quantum Cellular Automata at Nano Scale. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:291-296 [Conf]
  38. Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton
    Generalized Sensitization using Fault Tuples. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:297-303 [Conf]
  39. Abhishek Singh, Chintan Patel, Jim Plusquellic
    Fault Simulation Model for i{DDT} Testing: An Investigation. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:304-312 [Conf]
  40. Michael Nicolaidis, Nadir Achouri, Lorena Anghel
    A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:313-318 [Conf]
  41. Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris
    Cost-Driven Selection of Parity Trees. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:319-324 [Conf]
  42. Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff
    Soft Delay Error Effects in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:325-334 [Conf]
  43. Hans Eberle, Arvinderpal Wander, Nils Gura
    Testing Systems Wirelessly. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:335-340 [Conf]
  44. Brian Moore, Christopher J. Backhouse, Martin Margala
    Design of Wireless Sub-Micron Characterization System. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:341-346 [Conf]
  45. Tian-Wei Huang, Pei-Si Wu, Ren-Chieh Liu, Jeng-Han Tsai, Huei Wang, Tzi-Dar Chiueh
    Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:347-354 [Conf]
  46. Gang Zeng, Hideo Ito
    Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:355-360 [Conf]
  47. Erik Larsson, Julien Pouget, Zebo Peng
    Defect-Aware SOC Test Scheduling. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:361-366 [Conf]
  48. Md. Saffat Quasem, Sandeep K. Gupta
    Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:367-376 [Conf]
  49. Ashwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee
    Prediction of Analog Performance Parameters Using Oscillation Based Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:377-382 [Conf]
  50. Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
    An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:383-388 [Conf]
  51. Qingwei Wu, Michael S. Hsiao
    Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:389-405 [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002