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Conferences in DBLP

IEEE VLSI Test Symposium (vts)
2006 (conf/vts/2006)


  1. Organizing Committee. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]

  2. Forward. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]

  3. Steering Committee. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]

  4. Reviewers. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]

  5. Acknowledgments. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]

  6. Test Technology Technical Council (TTTC). [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]

  7. Test Technology Educational Progam (TTEP) Tutorials. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]

  8. Awards. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]

  9. Program Committee. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:- [Conf]
  10. Xijiang Lin, Janusz Rajski
    The Impacts of Untestable Defects on Transition Fault Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:2-7 [Conf]
  11. Kun Young Chung, Sandeep K. Gupta
    Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:8-15 [Conf]
  12. Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty
    Path Delay Fault Simulation on Large Industrial Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:16-23 [Conf]
  13. Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham
    A Scheme for On-Chip Timing Characterization. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:24-29 [Conf]
  14. Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh
    BIST for Network-on-Chip Interconnect Infrastructures. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:30-35 [Conf]
  15. Vishal Suthar, Shantanu Dutt
    Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:36-43 [Conf]
  16. Phil Nigh
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:44- [Conf]
  17. Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan
    Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:46-51 [Conf]
  18. Minsik Cho, David Z. Pan
    PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:52-57 [Conf]
  19. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
    A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:58-65 [Conf]
  20. Ruifeng Guo, Subhasish Mitra, Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman
    Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:66-71 [Conf]
  21. Avijit Dutta, Nur A. Touba
    Iterative OPDD Based Signal Probability Calculation. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:72-77 [Conf]
  22. Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty
    Silicon Evaluation of Logic Proximity Bridge Patterns. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:78-85 [Conf]
  23. Rubin A. Parekhji
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:86-87 [Conf]
  24. Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
    Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:88-93 [Conf]
  25. Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic
    A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:94-99 [Conf]
  26. Khadija Stewart, Spyros Tragoudas
    Interconnect Testing for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:100-107 [Conf]
  27. O. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    An Overview of Failure Mechanisms in Embedded Flash Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:108-113 [Conf]
  28. Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu
    A Built-In Self-Repair Scheme for NOR-Type Flash Memory. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:114-119 [Conf]
  29. Gurgen Harutunyan, Valery A. Vardanian, Y. Zorian Zorian
    Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:120-127 [Conf]
  30. Cheng-Wen Wu
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:128-129 [Conf]
  31. Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
    An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:130-135 [Conf]
  32. Rasit Onur Topaloglu
    Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:136-142 [Conf]
  33. Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
    BIST Pretest of ICs: Risks and Benefits. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:142-149 [Conf]
  34. Bernard Courtois
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:150-151 [Conf]
  35. Ajay Khoche
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:152-153 [Conf]
  36. Yervant Zorian, Dennis Wassung
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:154-155 [Conf]
  37. Erik Chmelar, Edward J. McCluskey
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:156-157 [Conf]
  38. Praveen Parvathala
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:158-159 [Conf]
  39. Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami
    Improved Handling of False and Multicycle Paths in ATPG. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:160-165 [Conf]
  40. Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    On the Automation of the Test Flow of Complex SoCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:166-171 [Conf]
  41. Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli
    Improving Gate-Level ATPG by Traversing Concurrent EFSMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:172-179 [Conf]
  42. Ashutosh Sharma, Anura P. Jayasumana, Yashwant K. Malaiya
    X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:180-185 [Conf]
  43. Rong Zhang, Zeljko Zilic, Katarzyna Radecka
    Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:186-191 [Conf]
  44. Vishwanath Natarajan, Soumendu Bhattacharya, Abhijit Chatterjee
    Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:192-199 [Conf]
  45. Kazumi Hatayama
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:200-201 [Conf]
  46. Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
    Design Optimization for Robustness to Single Event Upsets. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:202-207 [Conf]
  47. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterj
    Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:208-213 [Conf]
  48. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:214-221 [Conf]
  49. Ganesh Srinivasan, Abhijit Chatterjee, Friedrich Taenzler
    Alternate Loop-Back Diagnostic Tests for Wafer-Level Diagnosis of Modern Wireless Transceivers using Spectral Signatures. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:222-227 [Conf]
  50. Qi Wang, Mani Soma
    RF Front-end System Gain and Linearity Built-in Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:228-233 [Conf]
  51. Hsieh-Hung Hsieh, Liang-Hung Lu
    Integrated CMOS Power Sensors for RF BIST Applications. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:234-239 [Conf]
  52. Davide Appello
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:240-241 [Conf]
  53. Wojciech Rajski, Janusz Rajski
    Modular Compactor of Test Responses. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:242-251 [Conf]
  54. Jinkyu Lee, Nur A. Touba
    Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:252-257 [Conf]
  55. Vishnu C. Vimjam, Michael S. Hsiao
    Efficient Fault Collapsing via Generalized Dominance Relations. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:258-265 [Conf]
  56. Xinyue Fan, Will Moore, Camelia Hora, Mario H. Konijnenburg, Guido Gronthoud
    A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:266-271 [Conf]
  57. Fang Liu, Plamen K. Nikolov, Sule Ozev
    Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:272-277 [Conf]
  58. Mingjing Chen, Hosam Haggag, Alex Orailoglu
    Decision Tree Based Mismatch Diagnosis in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:278-285 [Conf]
  59. Michael Nicolaidis
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:286-287 [Conf]
  60. Ajay Khoche, Peter Muhmenthaler
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:288-289 [Conf]
  61. Andreas G. Veneris, Yiorgos Makris
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:290-291 [Conf]
  62. Kee Sup Kim, Mohammad Tehranipoor
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:292-293 [Conf]
  63. Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
    A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:294-299 [Conf]
  64. Huawei Li, Pei-Fu Shen, Xiaowei Li
    Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:300-305 [Conf]
  65. Jais Abraham, Uday Goel, Arun Kumar
    Multi-Cycle Sensitizable Transition Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:306-313 [Conf]
  66. Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro
    A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:314-319 [Conf]
  67. Sai Raghuram Durbha, Amit Laknaur, Haibo Wang
    Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:320-325 [Conf]
  68. Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell
    Functional Test of Field Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:326-333 [Conf]
  69. Yervant Zorian, Bruce C. Kim
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:334-335 [Conf]
  70. Richard Putman, Rahul Gawde
    Enhanced Timing-Based Transition Delay Testing for Small Delay Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:336-342 [Conf]
  71. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
    Scan Tests with Multiple Fault Activation Cycles for Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:343-348 [Conf]
  72. Adit D. Singh, Gefu Xu
    Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:349-357 [Conf]
  73. Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
    Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:358-363 [Conf]
  74. Jason G. Brown, R. D. (Shawn) Blanton
    Exploiting Regularity for Inductive Fault Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:364-369 [Conf]
  75. Reza M. Rad, Mohammad Tehranipoor
    SCT: An Approach For Testing and Configuring Nanoscale Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:370-377 [Conf]
  76. James Tschanz
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:378-379 [Conf]
  77. Bharath Seshadri, Xiaoming Yu, Srikanth Venkataraman
    Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:380-385 [Conf]
  78. Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
    A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:386-391 [Conf]
  79. Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy
    Dominance Based Analysis for Large Volume Production Fail Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:392-399 [Conf]
  80. C.-Y. Kuo, J.-L. Huang
    A Period Tracking Based On-Chip Sinusoidal Jitter Extraction Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:400-405 [Conf]
  81. Haralampos-G. D. Stratigopoulos, Yiorgos Makris
    Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:406-411 [Conf]
  82. Hongjoong Shin, Byoungho Kim, Jacob A. Abraham
    Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:412-419 [Conf]
  83. R. Chandramouli
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:420-421 [Conf]
  84. Rajesh Galivanche, Bob Gottlieb
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:422-423 [Conf]
  85. André Ivanov
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:424-425 [Conf]
  86. Ajay Khoche, Mike Rodgers, Pete O'Neil
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:426- [Conf]
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