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Conferences in DBLP

IEEE VLSI Test Symposium (vts)
2007 (conf/vts/2007)

  1. Erkan Acar, Sule Ozev, Kevin B. Redmond
    A Low-Cost RF MIMO Test Method Using a Single Measurement Set-up. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:3-8 [Conf]
  2. Haralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris
    Non-RF to RF Test Correlation Using Learning Machines: A Case Study. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:9-14 [Conf]
  3. Marcelo Negreiros, Adão Antônio de Souza Jr., Luigi Carro, Altamiro Amadeu Susin
    RF Digital Signal Generation Beyond Nyquist. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:15-22 [Conf]
  4. Soumitra Bose, Vishwani D. Agrawal
    Delay Test Quality Evaluation Using Bounded Gate Delays. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:23-28 [Conf]
  5. Bram Kruseman, Ananta K. Majhi, Guido Gronthoud
    On Performance Testing with Path Delay Patterns. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:29-34 [Conf]
  6. K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula
    Power Virus Generation Using Behavioral Models of Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:35-42 [Conf]
  7. O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:47-52 [Conf]
  8. Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu
    SDRAM Delay Fault Modeling and Performance Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:53-58 [Conf]
  9. Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
    Optimizing Test Length for Soft Faults in DRAM Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:59-66 [Conf]
  10. Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
    Minimizing the Impact of Scan Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:67-74 [Conf]
  11. Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
    Low Power Embedded Deterministic Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:75-83 [Conf]
  12. Anshuman Chandra, Haihua Yan, Rohit Kapur
    Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:84-92 [Conf]
  13. Claude Thibeault
    On a New Outlier Rejection Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:97-103 [Conf]
  14. Hyun Choi, Donghoon Han, Abhijit Chatterjee
    Enhanced Resolution Jitter Testing Using Jitter Expansion. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:104-109 [Conf]
  15. Hsiang-Hui Huang, Ching-Hwa Cheng
    Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:110-118 [Conf]
  16. Amit Laknaur, Rui Xiao, Haibo Wang
    A Programmable Window Comparator for Analog Online Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:119-124 [Conf]
  17. Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee
    Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:125-130 [Conf]
  18. X. Ma, Jing Huang, Fabrizio Lombardi
    Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:131-140 [Conf]
  19. D. Arumi, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:145-150 [Conf]
  20. Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou
    Handling Pattern-Dependent Delay Faults in Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:151-157 [Conf]
  21. Rosa Rodríguez-Montañés, D. Arumi, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Full Open Defects in Interconnecting Lines. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:158-166 [Conf]
  22. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:167-172 [Conf]
  23. Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland
    An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:173-178 [Conf]
  24. Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
    Supply Voltage Noise Aware ATPG for Transition Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:179-186 [Conf]
  25. Kyoung Youn Cho, Edward J. McCluskey
    Test Set Reordering Using the Gate Exhaustive Test Metric. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:199-204 [Conf]
  26. Jennifer Dworak
    An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:205-210 [Conf]
  27. Richard Putman, Nur A. Touba
    Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:211-218 [Conf]
  28. Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
    Accelerating Diagnosis via Dominance Relations between Sets of Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:219-224 [Conf]
  29. Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang
    Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:225-230 [Conf]
  30. Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang
    Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:231-238 [Conf]
  31. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi
    A UML Based System Level Failure Rate Assessment Technique for SoC Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:243-248 [Conf]
  32. John P. Hayes, Ilia Polian, Bernd Becker
    An Analysis Framework for Transient-Error Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:249-255 [Conf]
  33. Brian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano
    Case Study: Soft Error Rate Analysis in Storage Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:256-264 [Conf]
  34. Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware
    Silicon Evaluation of Static Alternative Fault Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:265-270 [Conf]
  35. Simon Wilson, Ben Flood, Suresh Goyal, Jim Mosher, Susan Bergin, Joseph O'Brien, Robert Kennedy
    Parameter Estimation for a Model with Both Imperfect Test and Repair. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:271-276 [Conf]
  36. Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra
    Circuit Failure Prediction and Its Application to Transistor Aging. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:277-286 [Conf]
  37. Byoungho Kim, Zhenhai Fu, Jacob A. Abraham
    Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:291-296 [Conf]
  38. V. Natarajan, G. Srinivasan, A. Chatterjee, Craig Force
    Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:297-302 [Conf]
  39. Le Jin, Degang Chen, Randall L. Geiger
    Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:303-310 [Conf]
  40. N. Honarmand, A. Shahabi, H. Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi
    High Level Synthesis of Degradable ASICs Using Virtual Binding. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:311-317 [Conf]
  41. Jian Kang, Sharad C. Seth, Vijay Gangaram
    Efficient RTL Coverage Metric for Functional Test Selection. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:318-324 [Conf]
  42. Kedarnath J. Balakrishnan, Lei Fang
    RTL Test Point Insertion to Reduce Delay Test Volume. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:325-332 [Conf]
  43. Avijit Dutta, Nur A. Touba
    Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:349-354 [Conf]
  44. Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen
    A Built-In Self-Repair Scheme for Multiport RAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:355-360 [Conf]
  45. A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
    Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:361-368 [Conf]
  46. Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
    Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:369-374 [Conf]
  47. Jaehoon Song, Piljae Min, HyunBean Yi, Sungju Park
    Design of Test Access Mechanism for AMBA-Based System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:375-380 [Conf]
  48. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
    TAM Design and Optimization for Transparency-Based SoC Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:381-388 [Conf]
  49. T.-L. Hung, J.-L. Huang
    A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:389-394 [Conf]
  50. Rajarajan Senguttuvan, Abhijit Chatterjee
    Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:395-400 [Conf]
  51. Yen-Chih Huang, Hsieh-Hung Hsieh, Liang-Hung Lu
    A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:401-408 [Conf]
  52. Peter Wohl, A. Waicukauski, Sanjay Patel
    Automated Design and Insertion of Optimal One-Hot Bus Encoders. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:409-415 [Conf]
  53. Irith Pomeranz, Sudhakar M. Reddy
    Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:416-421 [Conf]
  54. H. Rahaman, Jimson Mathew, B. K. Sikdar, Dhiraj K. Pradhan
    Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:422-430 [Conf]
  55. Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes
    DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:435-440 [Conf]
  56. Cecilia Metra, Martin Omaña, T. M. Mak, S. Tam
    Novel Approach to Clock Fault Testing for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:441-446 [Conf]
  57. Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
    At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:447-454 [Conf]
  58. Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
    VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:455-460 [Conf]
  59. Chunsheng Liu, Yu Huang
    Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:461-468 [Conf]
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