Conferences in DBLP
Erkan Acar , Sule Ozev , Kevin B. Redmond A Low-Cost RF MIMO Test Method Using a Single Measurement Set-up. [Citation Graph (0, 0)][DBLP ] Conf ] Haralampos-G. D. Stratigopoulos , Petros Drineas , Mustapha Slamani , Yiorgos Makris Non-RF to RF Test Correlation Using Learning Machines: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Negreiros , Adão Antônio de Souza Jr. , Luigi Carro , Altamiro Amadeu Susin RF Digital Signal Generation Beyond Nyquist. [Citation Graph (0, 0)][DBLP ] Conf ] Soumitra Bose , Vishwani D. Agrawal Delay Test Quality Evaluation Using Bounded Gate Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Bram Kruseman , Ananta K. Majhi , Guido Gronthoud On Performance Testing with Path Delay Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] K. Najeeb , Vishnu Vardhan Reddy Konda , Siva Kumar Sastry Hari , V. Kamakoti , Vivekananda M. Vedula Power Virus Generation Using Behavioral Models of Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] O. Ginez , Jean Michel Daga , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Tsao Hsing , Chun-Chieh Huang , Jen-Chieh Yeh , Cheng-Wen Wu SDRAM Delay Fault Modeling and Performance Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Zaid Al-Ars , Said Hamdioui , Georgi Gaydadjiev Optimizing Test Length for Soft Faults in DRAM Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , John A. Waicukauski , Rohit Kapur , S. Ramnath , Emil Gizdarski , Thomas W. Williams , P. Jaini Minimizing the Impact of Scan Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Dariusz Czysz , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer Low Power Embedded Deterministic Test. [Citation Graph (0, 0)][DBLP ] Conf ] Anshuman Chandra , Haihua Yan , Rohit Kapur Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Thibeault On a New Outlier Rejection Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Hyun Choi , Donghoon Han , Abhijit Chatterjee Enhanced Resolution Jitter Testing Using Jitter Expansion. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiang-Hui Huang , Ching-Hwa Cheng Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Laknaur , Rui Xiao , Haibo Wang A Programmable Window Comparator for Analog Online Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Maryam Ashouei , Soumendu Bhattacharya , Abhijit Chatterjee Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors. [Citation Graph (0, 0)][DBLP ] Conf ] X. Ma , Jing Huang , Fabrizio Lombardi Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets. [Citation Graph (0, 0)][DBLP ] Conf ] D. Arumi , Rosa Rodríguez-Montañés , Joan Figueras , Stefan Eichenberger , Camelia Hora , Bram Kruseman , Maurice Lousberg , Ananta K. Majhi Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Jyun-Wei Chen , Ying-Yen Chen , Jing-Jia Liou Handling Pattern-Dependent Delay Faults in Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Rosa Rodríguez-Montañés , D. Arumi , Joan Figueras , Stefan Eichenberger , Camelia Hora , Bram Kruseman , Maurice Lousberg , Ananta K. Majhi Diagnosis of Full Open Defects in Interconnecting Lines. [Citation Graph (0, 0)][DBLP ] Conf ] V. R. Devanathan , C. P. Ravikumar , V. Kamakoti Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Iyengar , Kenneth Pichamuthu , Andrew Ferko , Frank Woytowich , David E. Lackey , Gary Grise , Mark Taylor , Mike Degregorio , Steven F. Oakland An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Nisar Ahmed , Mohammad Tehranipoor , Vinay Jayaram Supply Voltage Noise Aware ATPG for Transition Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Kyoung Youn Cho , Edward J. McCluskey Test Set Reordering Using the Gate Exhaustive Test Metric. [Citation Graph (0, 0)][DBLP ] Conf ] Jennifer Dworak An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Putman , Nur A. Touba Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Rajsekhar Adapa , Spyros Tragoudas , Maria K. Michael Accelerating Diagnosis via Dominance Relations between Sets of Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zou , Wu-Tung Cheng , Sudhakar M. Reddy , Huaxing Tang Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. [Citation Graph (0, 0)][DBLP ] Conf ] Vishnu C. Vimjam , M. Enamul Amyeen , Ruifeng Guo , Srikanth Venkataraman , Michael S. Hsiao , Kai Yang Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Hosseinabady , Mohammad Hossein Neishaburi , Pejman Lotfi-Kamran , Zainalabedin Navabi A UML Based System Level Failure Rate Assessment Technique for SoC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Hayes , Ilia Polian , Bernd Becker An Analysis Framework for Transient-Error Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Mullins , Hossein Asadi , Mehdi Baradaran Tahoori , David R. Kaeli , Kevin Granlund , Rudy Bauer , Scott Romano Case Study: Soft Error Rate Analysis in Storage Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Schuermyer , Jewel Pangilinan , Jay Jahangiri , Martin Keim , Janusz Rajski , Brady Benware Silicon Evaluation of Static Alternative Fault Models. [Citation Graph (0, 0)][DBLP ] Conf ] Simon Wilson , Ben Flood , Suresh Goyal , Jim Mosher , Susan Bergin , Joseph O'Brien , Robert Kennedy Parameter Estimation for a Model with Both Imperfect Test and Repair. [Citation Graph (0, 0)][DBLP ] Conf ] Mridul Agarwal , Bipul C. Paul , Ming Zhang , Subhasish Mitra Circuit Failure Prediction and Its Application to Transistor Aging. [Citation Graph (0, 0)][DBLP ] Conf ] Byoungho Kim , Zhenhai Fu , Jacob A. Abraham Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] V. Natarajan , G. Srinivasan , A. Chatterjee , Craig Force Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios. [Citation Graph (0, 0)][DBLP ] Conf ] Le Jin , Degang Chen , Randall L. Geiger Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal. [Citation Graph (0, 0)][DBLP ] Conf ] N. Honarmand , A. Shahabi , H. Sohofi , Maghsoud Abbaspour , Zainalabedin Navabi High Level Synthesis of Degradable ASICs Using Virtual Binding. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Kang , Sharad C. Seth , Vijay Gangaram Efficient RTL Coverage Metric for Functional Test Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Kedarnath J. Balakrishnan , Lei Fang RTL Test Point Insertion to Reduce Delay Test Volume. [Citation Graph (0, 0)][DBLP ] Conf ] Avijit Dutta , Nur A. Touba Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. [Citation Graph (0, 0)][DBLP ] Conf ] Tsu-Wei Tseng , Chun-Hsien Wu , Yu-Jen Huang , Jin-Fu Li , Alex Pao , Kevin Chiu , Eliot Chen A Built-In Self-Repair Scheme for Multiport RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] A. Ney , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Edison Yu , Tomokazu Yoneda , Danella Zhao , Hideo Fujiwara Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jaehoon Song , Piljae Min , HyunBean Yi , Sungju Park Design of Test Access Mechanism for AMBA-Based System-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Tomokazu Yoneda , Akiko Shuto , Hideyuki Ichihara , Tomoo Inoue , Hideo Fujiwara TAM Design and Optimization for Transparency-Based SoC Test. [Citation Graph (0, 0)][DBLP ] Conf ] T.-L. Hung , J.-L. Huang A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarajan Senguttuvan , Abhijit Chatterjee Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Yen-Chih Huang , Hsieh-Hung Hsieh , Liang-Hung Lu A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , A. Waicukauski , Sanjay Patel Automated Design and Insertion of Optimal One-Hot Bus Encoders. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. [Citation Graph (0, 0)][DBLP ] Conf ] H. Rahaman , Jimson Mathew , B. K. Sikdar , Dhiraj K. Pradhan Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre M. Amory , Frederico Ferlini , Marcelo Lubaszewski , Fernando Moraes DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Martin Omaña , T. M. Mak , S. Tam Novel Approach to Clock Fault Testing for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Matthieu Tuna , Mounir Benabdenbi , Alain Greiner At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. [Citation Graph (0, 0)][DBLP ] Conf ] Somnath Paul , Rajat Subhra Chakraborty , Swarup Bhunia VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Chunsheng Liu , Yu Huang Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance. [Citation Graph (0, 0)][DBLP ] Conf ] 