Conferences in DBLP

Workshop on Memory Performance Issues (wmpi)
2004 (conf/wmpi/2004)

1. Magnus Ekman, Per Stenström
   A case for multi-level main memory. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:1-8 [Conf]
   
2. Erik G. Hallnor, Steven K. Reinhardt
   A compressed memory hierarchy using an indirect index cache. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:9-15 [Conf]
   
3. Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. Kuntz, Peter M. Kogge
   A low cost, multithreaded processing-in-memory system. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:16-22 [Conf]
   
4. Collin McCurdy, Charles N. Fischer
   A localizing directory coherence protocol. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:23-29 [Conf]
   
5. Faye A. Briggs, Suresh Chittor, Kai Cheng
   Micro-architecture techniques in the intel E8870 scalable memory controller. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:30-36 [Conf]
   
6. Stephen Somogyi, Thomas F. Wenisch, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi
   Memory coherence activity prediction in commercial workloads. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:37-45 [Conf]
   
7. José González, Fernando Latorre, Antonio González
   Cache organizations for clustered microarchitectures. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:46-55 [Conf]
   
8. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt
   Understanding the effects of wrong-path memory references on processor performance. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:56-64 [Conf]
   
9. Muhamed F. Mudawar
   Scalable cache memory design for large-scale SMT architectures. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:65-71 [Conf]
   
10. Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero
    Evaluating kilo-instruction multiprocessors. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:72-79 [Conf]
    
11. Chitra Natarajan, Bruce Christenson, Faye A. Briggs
    A study of performance impact of memory controller features in multi-processor server environment. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:80-87 [Conf]
    
12. G. Surendra, Subhasis Banerjee, S. K. Nandy
    On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:88-95 [Conf]
    
13. Doron Nakar, Shlomo Weiss
    Selective main memory compression by identifying program phase changes. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:96-101 [Conf]
    
14. Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher
    A low-power memory hierarchy for a fully programmable baseband processor. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:102-106 [Conf]
    
15. Irina Chihaia, Thomas R. Gross
    An analytical model for software-only main memory compression. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:107-113 [Conf]
    
16. Lars Wehmeyer, Urs Helmig, Peter Marwedel
    Compiler-optimized usage of partitioned memories. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:114-120 [Conf]
    
17. Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato
    SCIMA-SMP: on-chip memory processor architecture for SMP. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:121-128 [Conf]
    
18. Ramesh V. Peri, John Fernando, Ravi Kolagotla
    Addressing mode driven low power data caches for embedded processors. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:129-135 [Conf]
    
19. Steven T. Gabriel, David S. Wise
    The Opie compiler from row-major source to Morton-ordered matrices. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:136-144 [Conf]