Conferences in DBLP
Pen-Chung Yew A Compiler Framework for Supporting Speculative Multicore Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Kunio Uchiyama Power-Efficient Heterogeneous Multicore Technology for Digital Convergence. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng Wang , Shiliang Hu , Ho-Seop Kim , Sreekumar R. Nair , Mauricio Breternitz Jr. , Zhiwei Ying , Youfeng Wu StarDBT: An Efficient Multi-platform Dynamic Binary Translation System. [Citation Graph (0, 0)][DBLP ] Conf ] Arpad Gellert , Adrian Florea , Maria Vintan , Colin Egan , Lucian N. Vintan Unbiased Branches: An Open Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Liu , Hong An , Bo Liang , Li Wang An Online Profile Guided Optimization Approach for Speculative Parallel Threading. [Citation Graph (0, 0)][DBLP ] Conf ] Jinpyo Kim , Wei-Chung Hsu , Pen-Chung Yew , Sreekumar R. Nair , Robert Y. Geva Entropy-Based Profile Characterization and Classification for Automatic Profile Management. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Deng , Xuejun Yang , Xiaobo Yan , Kun Zeng Laplace Transformation on the FT64 Stream Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Lian Li 0002 , Hui Wu , Hui Feng , Jingling Xue Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Sang Lyul Min , Eyee Hyun Nam , Young Hee Lee Evolution of NAND Flash Memory Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Wang , Xiaowen Chen , Shuming Chen , Xing Fang , Shuwei Sun FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Piquet , Olivier Rochecouste , André Seznec Exploiting Single-Usage for Effective Memory Management. [Citation Graph (0, 0)][DBLP ] Conf ] Kang Yi , Shih-Yang Cheng , Young-Hwan Park , Fadi J. Kurdahi , Ahmed M. Eltawil An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Minyeol Seo , Ha Seok Kim , Ji Chan Maeng , Jimin Kim , Minsoo Ryu An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Reza Moraveji , Hamid Sarbazi-Azad , Maghsoud Abbaspour Optimal Placement of Frequently Accessed IPs in Mesh NoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Jaehoon Song , HyunBean Yi , Juhee Han , Sungju Park An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Sang-Hoon Ryu , Doo-Kwon Baik Performance of Keyword Connection Algorithm in Nested Mobility Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyofumi Tanaka , Takenori Fujita Leakage Energy Reduction in Cache Memory by Software Self-invalidation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel C. Vanderster , Amirali Baniasadi , Nikitas J. Dimopoulos Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Sang Jeong Lee , Hae-Kag Lee , Pen-Chung Yew Runtime Performance Projection Model for Dynamic Power Management. [Citation Graph (0, 0)][DBLP ] Conf ] Kaveh Aasaraai , Amirali Baniasadi A Power-Aware Alternative for the Perceptron Branch Predictor. [Citation Graph (0, 0)][DBLP ] Conf ] Akbar Sharifi , Hamid Sarbazi-Azad Power Consumption and Performance Analysis of 3D NoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Z. Zhang , Vijayan K. Asari A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels. [Citation Graph (0, 0)][DBLP ] Conf ] Shanq-Jang Ruan , Wei-te Lin Bipartition Architecture for Low Power JPEG Huffman Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Wensheng Tang , Shaogang Wang , Dan Wu , Wangqiu Kuang A SWP Specification for Sequential Image Processing Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Nan Wu , Qianming Yang , Mei Wen , Yi He , Changqing Xun , Chunyuan Zhang A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Dou , Jinbo Xu FPGA-Accelerated Active Shape Model for Real-Time People Tracking. [Citation Graph (0, 0)][DBLP ] Conf ] Partha Tirumalai , Yonghong Song , Spiros Kalogeropulos Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Shaoshan Liu , Jean-Luc Gaudiot Synchronization Mechanisms on Modern Multi-core Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbo Zeng , Kun Huang , Ming Wu , Weiwu Hu Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs. [Citation Graph (0, 0)][DBLP ] Conf ] Farshad Safaei , Ahmad Khonsari , Mahmood Fathy , N. Talebanfard , Mohamed Ould-Khaoua Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Thakur , William Gropp Open Issues in MPI Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Galluzzi , Enrique Vallejo , Adrián Cristal , Fernando Vallejo , Ramón Beivide , Per Stenström , James E. Smith , Mateo Valero Implicit Transactional Memory in Kilo-Instruction Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Li , Zhiying Wang , Xue-mi Zhao , Jian Ruan , Kui Dai Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. [Citation Graph (0, 0)][DBLP ] Conf ] Yongfeng Pan , Xiaoya Fan , Liqiang He , Deli Wang A Bypass Mechanism to Enhance Branch Predictor for SMT Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Emre Özer , Stuart Biles Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Yiyu Tan , Anthony S. Fong , Yang Xiaojian Architectural Solution to Object-Oriented Programming. [Citation Graph (0, 0)][DBLP ] Conf ] 