Conferences in DBLP
Walid A. Najjar Compiling code accelerators for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Gao , Stefan Kraemer , Rainer Leupers , Gerd Ascheid , Heinrich Meyr A fast and generic hybrid simulation approach using C virtual machine. [Citation Graph (0, 0)][DBLP ] Conf ] Florian Brandner , Dietmar Ebner , Andreas Krall Compiler generation from structural architecture descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Hugo Venturini , Frederic Riss , Jean-Claude Fernandez , Miguel Santana Non-transparent debugging for software-pipelined loops. [Citation Graph (0, 0)][DBLP ] Conf ] Sharad Singhai , MingYung Ko , Sanjay Jinturkar , Mayan Moudgill , John Glossner An integrated ARM and multi-core DSP simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Raimund Kirner SCCP/x: a compilation profile to support testing and verification of optimized code. [Citation Graph (0, 0)][DBLP ] Conf ] Luis A. Plana , Doug Edwards , Sam Taylor , Luis A. Tarazona , Andrew Bardsley Performance-driven syntax-directed synthesis of asynchronous processors. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Schäckeler , Weijia Shang Stack size reduction of recursive programs. [Citation Graph (0, 0)][DBLP ] Conf ] Hoeseok Yang , Sungchan Kim , Hae-woo Park , Jinwoo Kim , Soonhoi Ha Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Syed Imtiaz Haider , Leyla Nazhandali A hybrid code compression technique using bitmask and prefix encoding with enhanced dictionary selection. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin K. O'Brien Techniques for code and data management in the local stores of the cell processor. [Citation Graph (0, 0)][DBLP ] Conf ] Angel Dominguez , Nghi Nguyen , Rajeev Barua Recursive function data allocation to scratch-pad memory. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Baiocchi , Bruce R. Childers , Jack W. Davidson , Jason Hiser , Jonathan Misurda Fragment cache management for dynamic binary translators in embedded systems with scratchpad. [Citation Graph (0, 0)][DBLP ] Conf ] Nghi Nguyen , Angel Dominguez , Rajeev Barua Scratch-pad memory allocation without compiler support for java applications. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Hoover , Forrest Brewer , Timothy Sherwood Towards understanding architectural tradeoffs in MEMS closed-loop feedback control. [Citation Graph (0, 0)][DBLP ] Conf ] Karthik Ramani , Al Davis Application driven embedded system design: a face recognition case study. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Lin , Manjunath Kudlur , Scott A. Mahlke , Trevor N. Mudge Hierarchical coarse-grained stream compilation for software defined radio. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay K. Verma , Philip Brisk , Paolo Ienne Rethinking custom ISE identification: a new processor-agnostic method. [Citation Graph (0, 0)][DBLP ] Conf ] Huynh Phung Huynh , Joon Edward Sim , Tulika Mitra An efficient framework for dynamic reconfiguration of instruction-set customization. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Marongiu , Luca Benini , Mahmut T. Kandemir Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Chengmo Yang , Alex Orailoglu Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Roger Moussali , Nabil Ghanem , Mazen A. R. Saghir Supporting multithreading in configurable soft processor cores. [Citation Graph (0, 0)][DBLP ] Conf ] Dawoon Jung , Yoon-Hee Chae , Heeseung Jo , Jinsoo Kim , Joonwon Lee A group-based wear-leveling algorithm for large-capacity flash memory storage systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Zimmer , Stephen Roderick Hines , Prasad Kulkarni , Gary S. Tyson , David B. Whalley Facilitating compiler optimizations through the dynamic mapping of alternate register structures. [Citation Graph (0, 0)][DBLP ] Conf ] Ben Titzer , Jens Palsberg Vertical object layout and compression for fixed heaps. [Citation Graph (0, 0)][DBLP ] Conf ] Doosan Cho , Ilya Issenin , Nikil Dutt , Jonghee W. Yoon , Yunheung Paek Software controlled memory layout reorganization for irregular array access patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Weixing Ji , Feng Shi , Baojun Qiao A self-maintained memory module supporting DMM. [Citation Graph (0, 0)][DBLP ] Conf ] Rakesh Reddy , Peter Petrov Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor N. Mudge Multicore architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Brisk , Ajay K. Verma , Paolo Ienne An optimistic and conservative register assignment heuristic for chordal graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Carmen Badea , Alexandru Nicolau , Alexander V. Veidenbaum A simplified java bytecode compilation system for resource-constrained embedded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Vander Aa , Bingfeng Mei , Bjorn De Sutter A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Nagpal , Arvind Madan , Amrutur Bhardwaj , Y. N. Srikant INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations. [Citation Graph (0, 0)][DBLP ] Conf ] Jaw-Wei Chi , Chia-Lin Yang , Yi-Jung Chen , Jien-Jia Chen Cache leakage control mechanism for hard real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Rao , Sarma B. K. Vrudhula Performance optimal processor throttling under thermal constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad Zmily , Christos Kozyrakis A low power front-end for embedded processors using a block-aware instruction set. [Citation Graph (0, 0)][DBLP ] Conf ] 