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Conferences in DBLP

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) (cases)
2007 (conf/cases/2007)

  1. Walid A. Najjar
    Compiling code accelerators for FPGAs. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:1-2 [Conf]
  2. Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    A fast and generic hybrid simulation approach using C virtual machine. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:3-12 [Conf]
  3. Florian Brandner, Dietmar Ebner, Andreas Krall
    Compiler generation from structural architecture descriptions. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:13-22 [Conf]
  4. Hugo Venturini, Frederic Riss, Jean-Claude Fernandez, Miguel Santana
    Non-transparent debugging for software-pipelined loops. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:23-32 [Conf]
  5. Sharad Singhai, MingYung Ko, Sanjay Jinturkar, Mayan Moudgill, John Glossner
    An integrated ARM and multi-core DSP simulator. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:33-37 [Conf]
  6. Raimund Kirner
    SCCP/x: a compilation profile to support testing and verification of optimized code. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:38-42 [Conf]
  7. Luis A. Plana, Doug Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley
    Performance-driven syntax-directed synthesis of asynchronous processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:43-47 [Conf]
  8. Stefan Schäckeler, Weijia Shang
    Stack size reduction of recursive programs. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:48-52 [Conf]
  9. Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim, Soonhoi Ha
    Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:53-57 [Conf]
  10. Syed Imtiaz Haider, Leyla Nazhandali
    A hybrid code compression technique using bitmask and prefix encoding with enhanced dictionary selection. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:58-62 [Conf]
  11. Kevin K. O'Brien
    Techniques for code and data management in the local stores of the cell processor. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:63-64 [Conf]
  12. Angel Dominguez, Nghi Nguyen, Rajeev Barua
    Recursive function data allocation to scratch-pad memory. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:65-74 [Conf]
  13. Jose Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser, Jonathan Misurda
    Fragment cache management for dynamic binary translators in embedded systems with scratchpad. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:75-84 [Conf]
  14. Nghi Nguyen, Angel Dominguez, Rajeev Barua
    Scratch-pad memory allocation without compiler support for java applications. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:85-94 [Conf]
  15. Greg Hoover, Forrest Brewer, Timothy Sherwood
    Towards understanding architectural tradeoffs in MEMS closed-loop feedback control. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:95-102 [Conf]
  16. Karthik Ramani, Al Davis
    Application driven embedded system design: a face recognition case study. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:103-114 [Conf]
  17. Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevor N. Mudge
    Hierarchical coarse-grained stream compilation for software defined radio. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:115-124 [Conf]
  18. Ajay K. Verma, Philip Brisk, Paolo Ienne
    Rethinking custom ISE identification: a new processor-agnostic method. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:125-134 [Conf]
  19. Huynh Phung Huynh, Joon Edward Sim, Tulika Mitra
    An efficient framework for dynamic reconfiguration of instruction-set customization. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:135-144 [Conf]
  20. Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
    Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:145-149 [Conf]
  21. Chengmo Yang, Alex Orailoglu
    Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:150-154 [Conf]
  22. Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir
    Supporting multithreading in configurable soft processor cores. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:155-159 [Conf]
  23. Dawoon Jung, Yoon-Hee Chae, Heeseung Jo, Jinsoo Kim, Joonwon Lee
    A group-based wear-leveling algorithm for large-capacity flash memory storage systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:160-164 [Conf]
  24. Chris Zimmer, Stephen Roderick Hines, Prasad Kulkarni, Gary S. Tyson, David B. Whalley
    Facilitating compiler optimizations through the dynamic mapping of alternate register structures. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:165-169 [Conf]
  25. Ben Titzer, Jens Palsberg
    Vertical object layout and compression for fixed heaps. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:170-178 [Conf]
  26. Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek
    Software controlled memory layout reorganization for irregular array access patterns. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:179-188 [Conf]
  27. Weixing Ji, Feng Shi, Baojun Qiao
    A self-maintained memory module supporting DMM. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:189-197 [Conf]
  28. Rakesh Reddy, Peter Petrov
    Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:198-207 [Conf]
  29. Trevor N. Mudge
    Multicore architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:208- [Conf]
  30. Philip Brisk, Ajay K. Verma, Paolo Ienne
    An optimistic and conservative register assignment heuristic for chordal graphs. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:209-217 [Conf]
  31. Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum
    A simplified java bytecode compilation system for resource-constrained embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:218-228 [Conf]
  32. Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter
    A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:229-237 [Conf]
  33. Rahul Nagpal, Arvind Madan, Amrutur Bhardwaj, Y. N. Srikant
    INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:238-247 [Conf]
  34. Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jien-Jia Chen
    Cache leakage control mechanism for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:248-256 [Conf]
  35. Ravishankar Rao, Sarma B. K. Vrudhula
    Performance optimal processor throttling under thermal constraints. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:257-266 [Conf]
  36. Ahmad Zmily, Christos Kozyrakis
    A low power front-end for embedded processors using a block-aware instruction set. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:267-276 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002