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Conferences in DBLP
- Joshua Jaffe
A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:1-13 [Conf]
- Kerstin Lemke-Rust, Christof Paar
Gaussian Mixture Models for Higher-Order Side Channel Analysis. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:14-27 [Conf]
- Jean-Sébastien Coron, Emmanuel Prouff, Matthieu Rivain
Side Channel Cryptanalysis of a Higher Order Masking Scheme. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:28-44 [Conf]
- Markus Dichtl, Jovan Dj. Golic
High-Speed True Random Number Generation with Logic Gates Only. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:45-62 [Conf]
- Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrijen, Pim Tuyls
FPGA Intrinsic PUFs and Their Use for IP Protection. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:63-80 [Conf]
- Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard
Evaluation of the Masked Logic Style MDPL on a Prototype Chip. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:81-94 [Conf]
- Patrick Schaumont, Kris Tiri
Masking and Dual-Rail Logic Don't Add Up. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:95-106 [Conf]
- Benedikt Gierlichs
DPA-Resistance Without Routing Constraints? [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:107-120 [Conf]
- Mitsuru Matsui, Junko Nakajima
On the Power of Bitslice Implementation on Intel Core2 Processor. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:121-134 [Conf]
- Marc Joye
Highly Regular Right-to-Left Algorithms for Scalar Multiplication. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:135-147 [Conf]
- Hirotaka Yoshida, Dai Watanabe, Katsuyuki Okeya, Jun Kitahara, Hongjun Wu, Özgül Küçük, Bart Preneel
MAME: A Compression Function with Reduced Hardware Requirements. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:148-165 [Conf]
- Alex Biryukov, Andrey Bogdanov, Dmitry Khovratovich, Timo Kasper
Collision Attacks on AES-Based MAC: Alpha-MAC. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:166-180 [Conf]
- Christophe Clavier
Secret External Encodings Do Not Prevent Transient Fault Analysis. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:181-194 [Conf]
- Alex Biryukov, Dmitry Khovratovich
Two New Techniques of Side-Channel Cryptanalysis. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:195-208 [Conf]
- Owen Harrison, John Waldron
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:209-226 [Conf]
- Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli
Multi-gigabit GCM-AES Architecture Optimized for FPGAs. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:227-238 [Conf]
- Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto
Arithmetic Operators for Pairing-Based Cryptography. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:239-255 [Conf]
- Kimmo U. Järvinen, Juha Forsten, Jorma Skyttä
FPGA Design of Self-certified Signature Verification on Koblitz Curves. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:256-271 [Conf]
- Daisuke Suzuki
How to Maximize the Potential of FPGA Resources for Modular Exponentiation. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:272-288 [Conf]
- Reouven Elbaz, David Champagne, Ruby B. Lee, Lionel Torres, Gilles Sassatelli, Pierre Guillemin
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:289-302 [Conf]
- Stefan Tillich, Johann Großschädl
Power Analysis Resistant AES Implementation with Instruction Set Extensions. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:303-319 [Conf]
- Michael Hutter, Stefan Mangard, Martin Feldhofer
Power and EM Attacks on Passive 13.56 MHz RFID Devices. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:320-333 [Conf]
- O. Savry, F. Pebay-Peyroula, F. Dehmas, G. Robert, J. Reverdy
RFID Noisy Reader How to Prevent from Eavesdropping on the Communication? [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:334-345 [Conf]
- Gerald DeJean, Darko Kirovski
RF-DNA: Radio-Frequency Certificates of Authenticity. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:346-363 [Conf]
- Tetsuya Izu, Jun Kogure, Takeshi Shimoyama
CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:364-377 [Conf]
- Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater
Collision Search for Elliptic Curve Discrete Logarithm over GF(2 m ) with FPGA. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:378-393 [Conf]
- Andrey Bogdanov, Thomas Eisenbarth, Andy Rupp
A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:394-412 [Conf]
- Bruno Robisson, Pascal Manet
Differential Behavioral Analysis. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:413-426 [Conf]
- François Macé, François-Xavier Standaert, Jean-Jacques Quisquater
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:427-442 [Conf]
- Christophe Clavier, Jean-Sébastien Coron
On the Implementation of a Fast Prime Generation Algorithm. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:443-449 [Conf]
- Andrey Bogdanov, Lars R. Knudsen, Gregor Leander, Christof Paar, Axel Poschmann, Matthew J. B. Robshaw, Yannick Seurin, C. Vikkelsoe
PRESENT: An Ultra-Lightweight Block Cipher. [Citation Graph (0, 0)][DBLP]
CHES, 2007, pp:450-466 [Conf]
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