Conferences in DBLP
Oh-Hyun Kwon Perspective of the Future Semiconductor Industry: Challenges and Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence D. Burns Designing a New Automotive DNA. [Citation Graph (0, 0)][DBLP ] Conf ] Jan M. Rabaey Design without Borders - A Tribute to the Legacy of A. Richard Newton. [Citation Graph (0, 0)][DBLP ] Conf ] Cynthia E. Irvine , Karl N. Levitt Trusted Hardware: Can It Be Trustworthy? [Citation Graph (0, 0)][DBLP ] Conf ] Steven Trimberger Trusted Design in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] G. Edward Suh , Srinivas Devadas Physical Unclonable Functions for Device Authentication and Secret Key Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Kris Tiri Side-Channel Attack Pitfalls. [Citation Graph (0, 0)][DBLP ] Conf ] Francine Bacchini , Greg Spirakis , Juan Antonio Carballo , Kurt Keutzer , Aart J. de Geus , Fu-Chieh Hsu , Kazu Yamada Megatrends and EDA 2017. [Citation Graph (0, 0)][DBLP ] Conf ] Walter H. Tibboel , Victor Reyes , Martin Klompstra , Dennis Alders System-Level Design Flow Based on a Functional Reference for HW and SW. [Citation Graph (0, 0)][DBLP ] Conf ] Hiren D. Patel , Sandeep K. Shukla Model-driven Validation of SystemC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Bishnupriya Bhattacharya , John Rose , Stuart Swan Language Extensions to SystemC: Process Control Constructs. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Huang , Sang-Il Han , Katalin Popovici , Lisane B. de Brisolara , Xavier Guerin , Lei Li , Xiaolang Yan , Soo-Ik Chae , Luigi Carro , Ahmed Amine Jerraya Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. [Citation Graph (0, 0)][DBLP ] Conf ] Zhengtao Yu , Xun Liu Design of Rotary Clock Based Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammet Mustafa Ozdal Escape Routing For Dense Pin Clusters In Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Minsik Cho , Hua Xiang , Ruchir Puri , David Z. Pan TROY: Track Router with Yield-driven Wire Planning. [Citation Graph (0, 0)][DBLP ] Conf ] Min Pan , Chris Chu IPR: An Integrated Placement and Routing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Flavio M. de Paula , Alan J. Hu An Effective Guidance Strategy for Abstraction-Guided Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Lovleen Bhatia , Jayesh Gaur , Praveen Tiwari , Raj S. Mitra , Sunil H. Matange Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Jiang Long , Andrew Seawright Synthesizing SVA Local Variables for Formal Verification. [Citation Graph (0, 0)][DBLP ] Conf ] De-Shiuan Chiou , Da-Cheng Juan , Yu-Ting Chen , Shih-Chieh Chang Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Gu , Sachin S. Sapatnekar , Chris H. Kim Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled R. Heloue , Navid Azizi , Farid N. Najm Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Li , Zhiping Yu Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Seomun , Jaehyun Kim , Youngsoo Shin Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth Venkataraman , Ruchir Puri , Steve Griffith , Ankush Oberai , Robert Madge , Greg Yeric , Walter Ng , Yervant Zorian Making Manufacturing Work For You. [Citation Graph (0, 0)][DBLP ] Conf ] Ümit Y. Ogras , Radu Marculescu , Puru Choudhary , Diana Marculescu Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Théodore Marescaux , Henk Corporaal Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT. [Citation Graph (0, 0)][DBLP ] Conf ] Zhonghai Lu , Ming Liu , Axel Jantsch Layered Switching for Networks on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Lap-Fai Leung , Chi-Ying Tsui Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands. [Citation Graph (0, 0)][DBLP ] Conf ] Assaf Shacham , Keren Bergman , Luca P. Carloni The Case for Low-Power Photonic Networks on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Shweta Srivastava , Jaijeet S. Roychowdhury Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Zhichun Wang , Xiaolue Lai , Jaijeet Roychowdhury PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Ramalingam , Ashish Kumar Singh , Sani R. Nassif , Michael Orshansky , David Z. Pan Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Suwen Yang , Mark R. Greenstreet Simulating Improbable Events. [Citation Graph (0, 0)][DBLP ] Conf ] Boyuan Yan , Sheldon X.-D. Tan , Pu Liu , Bruce McGaughy SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Min Zhao , Rajendran Panda , Ben Reschke , Yuhong Fu , Trudi Mewett , Sri Chandrasekaran , Savithri Sundareswaran , Shu Yan On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Behnam Amelifard , Massoud Pedram Optimal Selection of Voltage Regulator Modules in a Power Delivery Network. [Citation Graph (0, 0)][DBLP ] Conf ] Ravikishore Gandikota , Kaviraj Chopra , David Blaauw , Dennis Sylvester , Murat R. Becer Top-k Aggressors Sets in Delay Noise Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanyuan Jiang , Shiyan Hu , Weiping Shi A New Twisted Differential Line Structure in Global Bus Design. [Citation Graph (0, 0)][DBLP ] Conf ] Abinash Roy , Noha Mahmoud , Masud H. Chowdhury Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. [Citation Graph (0, 0)][DBLP ] Conf ] Moshe Y. Vardi Formal Techniques for SystemC Verification; Position Paper. [Citation Graph (0, 0)][DBLP ] Conf ] Anmol Mathur , Venkat Krishnaswamy Design for Verification in System-level Models and RTL. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Kasuya , Tesh Tesfaye Verification Methodologies in a TLM-to-RTL Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred Koelbl , Jerry R. Burch , Carl Pixley Memory Modeling in ESL-RTL Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Gila Kamhi , Sarah Miller , Stephen Bailey Mentor , Wolfgang H. Nebel , Y. C. Wong , Juergen Karmann , Enrico Macii , Stephen V. Kosonocky , Steve Curtis Early Power-Aware Design & Validation: Myth or Reality? [Citation Graph (0, 0)][DBLP ] Conf ] Yuan-Hao Chang , Jen-Wei Hsieh , Tei-Wei Kuo Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ram Kumar , Akhilesh Singhania , Andrew Castner , Eddie Kohler , Mani B. Srivastava A System For Coarse Grained Memory Protection In Tiny Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hakduran Koc , Mahmut T. Kandemir , Ehat Ercanli , Ozcan Ozturk Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors. [Citation Graph (0, 0)][DBLP ] Conf ] Liping Xue , Ozcan Ozturk , Mahmut T. Kandemir A Memory-Conscious Code Parallelization Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Ann Gordon-Ross , Frank Vahid A Self-Tuning Configurable Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. Burns , Mahesh Ketkar , Noel Menezes , Keith A. Bowman , James Tschanz , Vivek De Comparative Analysis of Conventional and Statistical Design Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Feng , Peng Li , Yaping Zhan Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Lerong Cheng , Jinjun Xiong , Lei He Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. [Citation Graph (0, 0)][DBLP ] Conf ] Amith Singhee , Rob A. Rutenbar Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Solomatnikov , Amin Firoozshahian , Wajahat Qadeer , Ofer Shacham , Kyle Kelley , Zain Asgar , Megan Wachs , Rehan Hameed , Mark Horowitz Chip Multi-Processor Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Edwards , Edward A. Lee The Case for the Precision Timed (PRET) Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Bogdan , Radu Marculescu Quantum-Like Effects in Network-on-Chip Buffers Behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Farinaz Koushanfar , Miodrag Potkonjak CAD-based Security, Cryptography, and Digital Rights Management. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Youngmin Kim , Saumil Shah , Dennis Sylvester Line-End Shortening is Not Always a Failure. [Citation Graph (0, 0)][DBLP ] Conf ] Steven P. Levitan You Can Get There From Here: Connectivity of Random Graphs on Grids. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Li , Kunhyuk Kang , Aditya Bansal , Kaushik Roy High Performance and Low Power Electronics on Flexible Substrate. [Citation Graph (0, 0)][DBLP ] Conf ] J. Liu , Ian O'Connor , David Navarro , Frédéric Gaffiot Novel CNTFET-based Reconfigurable Logic Gate Design. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Davare , Qi Zhu , Marco Di Natale , Claudio Pinello , Sri Kanajan , Alberto L. Sangiovanni-Vincentelli Period Optimization for Hard Real-time Distributed Automotive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andrei Hagiescu , Unmesh D. Bordoloi , Samarjit Chakraborty , Prahladavaradan Sampath , P. Vignesh V. Ganesan , S. Ramesh Performance Analysis of FlexRay-based ECU Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Juan R. Pimentel , Jason Paskvan Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application. [Citation Graph (0, 0)][DBLP ] Conf ] Zonghua Gu , Xiuqiang He , Mingxuan Yuan Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhang , Li Shang , Niraj K. Jha NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Hamed F. Dadgour , Kaustav Banerjee Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Changyun Zhu , Zhenyu (Peter) Gu , Li Shang , Robert P. Dick , Robert G. Knobel Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Cheng , Deming Chen , Martin D. F. Wong GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. [Citation Graph (0, 0)][DBLP ] Conf ] Tomasz S. Czajkowski , Stephen Dean Brown Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] S. Golshan , E. Bozorgzadeh Single-Event-Upset (SEU) Awareness in FPGA Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Brisk , Ajay K. Verma , Paolo Ienne , Hadi Parandeh-Afshar Enhancing FPGA Performance for Arithmetic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ruiming Chen , Hai Zhou Fast Min-Cost Buffer Insertion under Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Taylor , Larry T. Pileggi Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Rizzo , Hanno Melzner Concurrent Wire Spreading, Widening, and Filling. [Citation Graph (0, 0)][DBLP ] Conf ] Min-Chun Tsai , Daniel Zhang , Zongwu Tang Modeling Litho-Constrained Design Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Kunhyuk Kang , Kee-Jong Kim , Ahmad E. Islam , Mohammad Ashraful Alam , Kaushik Roy Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. [Citation Graph (0, 0)][DBLP ] Conf ] Wenping Wang , Shengqi Yang , Sarvesh Bhardwaj , Rakesh Vattikonda , Sarma B. K. Vrudhula , Frank Liu , Yu Cao The Impact of NBTI on the Performance of Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay V. Kumar , Chris H. Kim , Sachin S. Sapatnekar NBTI-Aware Synthesis of Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hartmut Hiller "There Is More Than Moore In Automotive ...". [Citation Graph (0, 0)][DBLP ] Conf ] Leonid B. Goldgeisser , Ernst Christen , Zhichao Deng Modeling Safe Operating Area in Hardware Description Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Dave Ferguson Autonomous Automobiles: Developing Cars That Drive Themselves. [Citation Graph (0, 0)][DBLP ] Conf ] Li-C. Wang , Pouria Bastani , Magdy S. Abadir Design-Silicon Timing Correlation A Data Mining Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Kip Killpack , Chandramouli V. Kashyap , Eli Chiprout Silicon Speedpath Measurement and Feedback into EDA flows. [Citation Graph (0, 0)][DBLP ] Conf ] Kanak Agarwal , Sani R. Nassif Characterizing Process Variation in Nanometer CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Nagata On-Chip Measurements Complementary to Design Flow for Integrity in SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay K. Verma , Philip Brisk , Paolo Ienne Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rebecca L. Collins , Luca P. Carloni Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System. [Citation Graph (0, 0)][DBLP ] Conf ] Jordi Cortadella , Michael Kishinevsky Synchronous Elastic Circuits with Early Evaluation and Token Counterflow. [Citation Graph (0, 0)][DBLP ] Conf ] Levent Aksoy , Eduardo A. C. da Costa , Paulo F. Flores , José C. Monteiro Optimization of Area in Digital FIR Filters using Gate-Level Metrics. [Citation Graph (0, 0)][DBLP ] Conf ] Igor Vytyaz , David C. Lee , Suihua Lu , Amit Mehrotra , Un-Ku Moon , Kartikeya Mayaram Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency. [Citation Graph (0, 0)][DBLP ] Conf ] Henry H. Y. Chan , Zeljko Zilic Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Dong , Peng Li Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical Preconditioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jaeha Kim , Kevin D. Jones , Mark A. Horowitz Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch. [Citation Graph (0, 0)][DBLP ] Conf ] Francine Bacchini , Daniel D. Gajski , Laurent Maillet-Contoz , Haruhisa Kashiwagi , Jack Donovan , Tommi Mäkeläinen , Jack Greenbaum , Rishiyur S. Nikhil TLM: Crossing Over From Buzz To Adoption. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Smith , Andrew Chien , Christopher Hegarty , Walden C. Rhines , Alberto L. Sangiovanni-Vincentelli , Frank Winters Electronics: The New Differential in the Automotive Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Tung-Chieh Chen , Ping-Hung Yuh , Yao-Wen Chang , Fwu-Juh Huang , Denny Liu MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Natarajan Viswanathan , Gi-Joon Nam , Charles J. Alpert , Paul Villarrubia , Haoxing Ren , Chris Chu RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. [Citation Graph (0, 0)][DBLP ] Conf ] Huaizhi Wu , Martin D. F. Wong Improving Voltage Assignment by Outlier Detection and Incremental Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Po-Hung Lin , Shyh-Chang Lin Analog Placement Based on Novel Symmetry-Island Formulation. [Citation Graph (0, 0)][DBLP ] Conf ] Raimund Kirner , Martin Schoeberl Modeling the Function Cache for Worst-Case Execution Time Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Fu Kao , Ing-Jer Huang , Chi-Hung Lin An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Shufu Mao , Tilman Wolf Hardware Support for Secure Processing in Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jude Angelo Ambrose , Roshan G. Ragel , Sri Parameswaran RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. [Citation Graph (0, 0)][DBLP ] Conf ] Piti Piyachon , Yan Luo Compact State Machines for High Performance Pattern Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Qunzeng Liu , Sachin S. Sapatnekar Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Choongyeun Cho , Daeik Kim , Jonghae Kim , Jean-Olivier Plouchart , Robert Trzcinski Statistical Framework for Technology-Model-Product Co-Design and Convergence. [Citation Graph (0, 0)][DBLP ] Conf ] Ying-Yen Chen , Jing-Jia Liou Extraction of Statistical Timing Profiles Using Test Data. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Sundaresan , Nihar R. Mahapatra An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires. [Citation Graph (0, 0)][DBLP ] Conf ] Michael E. Imhof , Christian G. Zoellin , Hans-Joachim Wunderlich , Nicolas Mäding , Jens Leenstra Scan Test Planning for Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoqing Wen , Kohei Miyase , Tatsuya Suzuki , Seiji Kajihara , Yuji Ohsumi , Kewal K. Saluja Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Nisar Ahmed , Mohammad Tehranipoor , Vinay Jayaram Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Mrugalski , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer New Test Data Decompressor for Low Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Razvan Racu , Arne Hamann , Rolf Ernst , Kai Richter Automotive Software Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Di Natale Virtual Platforms and Timing Analysis: Status, Challenges and Future Directions. [Citation Graph (0, 0)][DBLP ] Conf ] Antal Rajnak , Ajay Kumar Computer-aided Architecture Design & Optimized Implementation of Distributed Automotive EE Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kerry Bernstein , Paul Andry , Jerome Cann , Philip G. Emma , David Greenberg , Wilfried Haensch , Mike Ignatowski , Steve Koester , John Magerlein , Ruchir Puri , Albert Young Interconnects in the Third Dimension: Design Challenges for 3D ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Azad Naeemi , Reza Sarvari , James D. Meindl Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet Roychowdhury Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations. [Citation Graph (0, 0)][DBLP ] Conf ] Louis Scheffer CAD Implications of New Interconnect Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] HyoJung Han , Fabio Somenzi Alembic: An Efficient Algorithm for CNF Preprocessing. [Citation Graph (0, 0)][DBLP ] Conf ] Shujun Deng , Jinian Bian , Weimin Wu , Xiaoqing Yang , Yanni Zhao EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. [Citation Graph (0, 0)][DBLP ] Conf ] Ohad Shacham , Karen Yorav On-The-Fly Resolve Trace Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Satrajit Chatterjee , Alan Mishchenko , Robert K. Brayton , Andreas Kuehlmann On Resolution Proofs for Combinational Equivalence. [Citation Graph (0, 0)][DBLP ] Conf ] Jia-Wei Fang , Chin-Hsiung Hsu , Yao-Wen Chang An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Bharath , Ege Engin , Madhavan Swaminathan , Kazuhide Uriu , Toru Yamada Computationally Efficient Power Integrity Simulation for System-on-Package Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Yu , Chunta Chu , Lei He Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kiran Puttaswamy , Gabriel H. Loh Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Brent Goplen , Sachin S. Sapatnekar Placement of 3D ICs with Thermal and Interlayer Via Considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Lauren Sarno , Wen-mei W. Hwu , Craig Lund , Markus Levy , James R. Larus , James Reinders , Gordon Cameron , Chris Lennard , Takashi Yoshimori Corezilla: Build and Tame the Multicore Beast? [Citation Graph (0, 0)][DBLP ] Conf ] Ron Weiss Synthetic biology: from bacteria to stem cells. [Citation Graph (0, 0)][DBLP ] Conf ] Lingchong You Engineering synthetic killer circuits in bacteria. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey J. Tabor Programming Living Cells to Function as Massively Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Fett , Jehoshua Bruck , Marc D. Riedel Synthesizing Stochasticity in Biochemical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Talal Bonny , Jörg Henkel Instruction Splitting for Efficient Code Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Jui-Chin Chu , Wei-Chun Ku , Shu-Hsuan Chou , Tien-Fu Chen , Jiun-In Guo An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. [Citation Graph (0, 0)][DBLP ] Conf ] Maarten Wiggers , Marco Bekooij , Gerard J. M. Smit Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Changjiu Xian , Yung-Hsiang Lu , Zhiyuan Li Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution Time. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Bhojwani , Rabi N. Mahapatra A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Xu , Yubin Zhang , Krishnendu Chakrabarty SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Iwata , Tomokazu Yoneda , Hideo Fujiwara A DFT Method for Time Expansion Model at Register Transfer Level. [Citation Graph (0, 0)][DBLP ] Conf ] Dhiraj Goswami , Kun-Han Tsai , Mark Kassab , Janusz Rajski Test Generation in the Presence of Timing Exceptions and Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Mingoo Seok , Scott Hanson , Dennis Sylvester , David Blaauw Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hanson , Mingoo Seok , Dennis Sylvester , David Blaauw Nanometer Device Scaling in Subthreshold Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hedi Harizi , Robert HauBler , Markus Olbrich , Erich Barke Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ashesh Rastogi , Wei Chen , Sandip Kundu On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. [Citation Graph (0, 0)][DBLP ] Conf ] Yongsoo Joo , Youngjin Cho , Donghwa Shin , Naehyuck Chang Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Bobrek , JoAnn M. Paul , Donald E. Thomas Shared Resource Access Attributes for High-Level Contention Models. [Citation Graph (0, 0)][DBLP ] Conf ] Akash Kumar , Bart Mesman , Henk Corporaal , Bart D. Theelen , Yajun Ha A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Hallschmid , Resve Saleh Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Balaji Raman , Samarjit Chakraborty , Wei Tsang Ooi , Santanu Dutta Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution. [Citation Graph (0, 0)][DBLP ] Conf ] Francine Bacchini , Alan J. Hu , Tom Fitzpatrick , Rajeev Ranjan , David Lacey , Mercedes Tan , Andrew Piziali , Avi Ziv Verification Coverage: When is Enough, Enough? [Citation Graph (0, 0)][DBLP ] Conf ] Shekhar Borkar Thousand Core ChipsA Technology Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Anant Agarwal , Markus Levy The KILL Rule for Multicore. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-mei W. Hwu , Shane Ryoo , Sain-zee Ueng , John H. Kelm , Isaac Gelado , Sam S. Stone , Robert E. Kidd , Sara S. Baghsorkhi , Aqeel Mahesri , Stephanie C. Tsao , Nacho Navarro , Steven S. Lumetta , Matthew I. Frank , Sanjay J. Patel Implicitly Parallel Programming Models for Thousand-Core Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Darringer Multi-Core Design Automation Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Kyoung-Hwan Lim , Yonghwan Kim , Taewhan Kim Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil Dutt , Juanjo Noguera Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sander Stuijk , Twan Basten , Marc Geilen , Henk Corporaal Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Girish Venkataramani , Mihai Budiu , Tiberiu Chelcea , Seth Copen Goldstein Global Critical Path: A Tool for System-Level Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Pramod Chandraiah , Rainer Dömer Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification. 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