Conferences in DBLP
Tohru Furuyama Keynote address: Challenges of digital consumer and mobile SoC's: more Moore possible? [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1- [Conf ] Alan Naumann Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore's law? [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:2- [Conf ] Njuguna Njoroge , Jared Casper , Sewook Wee , Yuriy Teslyar , Daxia Ge , Christos Kozyrakis , Kunle Olukotun ATLAS: a chip-multiprocessor with transactional memory support. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:3-8 [Conf ] Fabio Campi , Antonio Deledda , Matteo Pizzotti , Luca Ciccarelli , Pier Luigi Rolandi , Claudio Mucci , Andrea Lodi , Arseni Vitkovski , Luca Vanzolini A dynamically adaptive DSP for heterogeneous reconfigurable platforms. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:9-14 [Conf ] Phillip Stanley-Marbell , Diana Marculescu An 0.9 × 1.2", low power, energy-harvesting system with custom multi-channel communication interface. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:15-20 [Conf ] Zhuan Ye , John Grosspietsch , Gokhan Memik Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:21-26 [Conf ] Ozgur Sinanoglu , Tsvetomir Petrov A non-intrusive isolation approach for soft cores. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:27-32 [Conf ] Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar Unknown blocking scheme for low control data volume and high observability. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:33-38 [Conf ] Quming Zhou , Kedarnath J. Balakrishnan Test cost reduction for SoC using a combined approach to test data compression and test scheduling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:39-44 [Conf ] Sying-Jyan Wang , Tung-Hua Yeh High-level test synthesis for delay fault testability. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:45-50 [Conf ] Traian Pop , Paul Pop , Petru Eles , Zebo Peng Bus access optimisation for FlexRay-based distributed embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:51-56 [Conf ] Nadathur Satish , Kaushik Ravindran , Kurt Keutzer A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:57-62 [Conf ] Chuan Lin , Aiguo Xie , Hai Zhou Design closure driven delay relaxation based on convex cost network flow. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:63-68 [Conf ] Varun Aggarwal , Una-May O'Reilly Simulation-based reusable posynomial models for MOS transistor parameters. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:69-74 [Conf ] Daniel Mueller , Helmut E. Graeb , Ulf Schlichtmann Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:75-80 [Conf ] Tom Eeckelaert , Raf Schoofs , Georges G. E. Gielen , Michiel Steyaert , Willy M. C. Sansen An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:81-86 [Conf ] Ömer Yetik , Orkun Saglamdemir , Selçuk Talay , Günhan Dündar Interactive presentation: A coefficient optimization and architecture selection tool for SigmaDelta modulators in MATLAB. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:87-92 [Conf ] Wei Zheng , Marco Di Natale , Claudio Pinello , Paolo Giusto , Alberto L. Sangiovanni-Vincentelli Synthesis of task and message activation models in real-time distributed automotive systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:93-98 [Conf ] Christopher Ostler , Karam S. Chatha An ILP formulation for system-level application mapping on network processor architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:99-104 [Conf ] Paolo Destro , Franco Fummi , Graziano Pravadelli A smooth refinement flow for co-designing HW and SW threads. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:105-110 [Conf ] Youssef N. Naguib , Rafik S. Guindi Speeding up SystemC simulation through process splitting. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:111-116 [Conf ] Akash Kumar , Andreas Hansson , Jos Huisken , Henk Corporaal Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:117-122 [Conf ] Florian Dittmann , Stefan Frank Hard real-time reconfiguration port scheduling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:123-128 [Conf ] Jin Cui , Qingxu Deng , Xiuqiang He , Zonghua Gu An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:129-134 [Conf ] Ahmed A. El Farag , Hatem M. El-Boghdadi , Samir I. Shaheen Improving utilization of reconfigurable resources using two dimensional compaction. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:135-140 [Conf ] Roman L. Lysecky Low-power warp processor for power efficient high-performance embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:141-146 [Conf ] Yang Qu , Juha-Pekka Soininen , Jari Nurmi Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:147-152 [Conf ] Mona Safar , Mohamed Shalan , M. Watheq El-Kharashi , Ashraf Salem Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:153-158 [Conf ] Markos Papadonikolakis , Vasilleios Pantazis , Athanasios Kakarountas Efficient high-performance ASIC implementation of JPEG-LS encoder. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:159-164 [Conf ] Yen-Jen Chang , Yuan-Hong Liao , Shanq-Jang Ruan Improve CAM power efficiency using decoupled match line scheme. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:165-170 [Conf ] André B. J. Kokkeler , Gerard J. M. Smit , Thijs Krol , Jan Kuper Cyclostationary feature detection on a tiled-SoC. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:171-176 [Conf ] C. Arbelo , Andreas Kanstein , Sebastián López , José Francisco López , Mladen Berekovic , Roberto Sarmiento , Jean-Yves Mignolet Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:177-182 [Conf ] Esra Sahin , Ilker Hamzaoglu Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:183-188 [Conf ] Ramanathan Narayanan , Daniel Honbo , Gokhan Memik , Alok N. Choudhary , Joseph Zambreno Interactive presentation: An FPGA implementation of decision tree classification. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:189-194 [Conf ] Nishant R. Srivastava Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:195-200 [Conf ] Zhanglei Wang , Krishnendu Chakrabarty , Seongmoon Wang SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:201-206 [Conf ] Anders Larsson , Erik Larsson , Petru Eles , Zebo Peng Optimized integration of test compression and sharing for SOC testing. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:207-212 [Conf ] Oliver Spang , Hans Martin von Staudt , Michael G. Wahl A sophisticated memory test engine for LCD display drivers. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:213-218 [Conf ] Thuyen Le , Tilman Glökler , Jason Baumgartner Formal verification of a pervasive interconnect bus system in a high-performance microprocessor. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:219-224 [Conf ] Ehab Anis , Nicola Nicolici Interactive presentation: Low cost debug architecture using lossy compression for silicon debug. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:225-230 [Conf ] Tomokazu Yoneda , Masahiro Imanishi , Hideo Fujiwara Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:231-236 [Conf ] Shekhar Borkar , Norman P. Jouppi , Per Stenström Microprocessors in the era of terascale integration. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:237-242 [Conf ] M. Zhang , M. Olbrich , D. Seider , M. Frerichs , H. Kinzelbach , E. Barke CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:243-248 [Conf ] Ghiath Al-Sammane , Mohamed H. Zaki , Sofiène Tahar A symbolic methodology for the verification of analog and mixed signal designs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:249-254 [Conf ] Dani Tannir , Roni Khazaka Efficient nonlinear distortion analysis of RF circuits. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:255-260 [Conf ] Jonathan Borremans , Ludwig De Locht , Piet Wambacq , Yves Rolain Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:261-266 [Conf ] J. Lataire , Gerd Vandersteen , Rik Pintelon Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:267-272 [Conf ] Simon Schliecker , Steffen Stein , Rolf Ernst Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:273-278 [Conf ] Hiren D. Patel , Sandeep K. Shukla Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:279-284 [Conf ] Marc Geilen , Twan Basten A calculator for Pareto points. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:285-290 [Conf ] Shuilong Huang , Huainan Ma , Zhihua Wang Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:291-296 [Conf ] Fei Gong , Xiaobo Wu Interactive presentation: System level power optimization of Sigma-Delta modulator. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:297-300 [Conf ] Leandro Soares Indrusiak , Andreas Thuy , Manfred Glesner Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:301-306 [Conf ] Soumya Eachempati , Arthur Nieuwoudt , Aman Gayasen , Narayanan Vijaykrishnan , Yehia Massoud Assessing carbon nanotube bundle interconnect for future FPGA architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:307-312 [Conf ] Scott Sirowy , Yonghui Wu , Stefano Lonardi , Frank Vahid Two-level microprocessor-accelerator partitioning. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:313-318 [Conf ] Anupam Chattopadhyay , W. Ahmed , Kingshuk Karuri , David Kammler , Rainer Leupers , Gerd Ascheid , Heinrich Meyr Design space exploration of partially re-configurable embedded processors. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:319-324 [Conf ] Hamid Noori , Farhad Mehdipour , Kazuaki Murakami , Koji Inoue , Maziar Goudarzi Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:325-330 [Conf ] Torben Brack , M. Alles , T. Lehnigk-Emden , Frank Kienle , Norbert Wehn , Nicola E. L'Insalata , Francesco Rossi , Massimo Rovini , Luca Fanucci Low complexity LDPC code decoders for next generation standards. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:331-336 [Conf ] John Dielissen , Andries Hekstra Non-fractional parallelism in LDPC decoder implementations. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:337-342 [Conf ] Weihuang Wang , Gwan Choi Minimum-energy LDPC decoder for real-time mobile application. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:343-348 [Conf ] Zahid Khan , Tughrul Arslan Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:349-354 [Conf ] Claudio Mucci , Luca Vanzolini , Fabio Campi , Mario Toma Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:355-360 [Conf ] Mohammad Hosseinabady , Atefe Dalirsani , Zainalabedin Navabi Using the inter- and intra-switch regularity in NoC switch testing. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:361-366 [Conf ] Kim Petersén , Johnny Öberg Toward a scalable test methodology for 2D-mesh Network-on-Chips. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:367-372 [Conf ] Oussama Laouamri , Chouki Aktouf Remote testing and diagnosis of System-on-Chips using network management frameworks. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:373-378 [Conf ] Qubo Hu , Arnout Vandecappelle , Per Gunnar Kjeldsberg , Francky Catthoor , Martin Palkovic Fast memory footprint estimation based on maximal dependency vector calculation. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:379-384 [Conf ] Hongwei Zhu , Ilie I. Luican , Florin Balasa Mapping multi-dimensional signals into hierarchical memory organizations. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:385-390 [Conf ] Srikanth Kurra , Neeraj Kumar Singh , Preeti Ranjan Panda The impact of loop unrolling on controller delay in high level synthesis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:391-396 [Conf ] Scott Sirowy , Yonghui Wu , Stefano Lonardi , Frank Vahid Clock-frequency assignment for multiple clock domain systems-on-a-chip. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:397-402 [Conf ] Siddharth Garg , Diana Marculescu Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:403-408 [Conf ] Michael Glaß , Martin Lukasiewycz , Thilo Streichert , Christian Haubelt , Jürgen Teich Interactive presentation: Reliability-aware system synthesis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:409-414 [Conf ] Pengbo Sun , Ying Wei , Alex Doboli Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:415-420 [Conf ] Gianvito Matarrese , Cristoforo Marzocca , Francesco Corsi , Stefano D'Amico , Andrea Baschirotto Experimental validation of a tuning algorithm for high-speed filters. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:421-426 [Conf ] Hamed Aminzadeh , Mohammad Danaie , Reza Lotfi Design of high-resolution MOSFET-only pipelined ADCs with digital calibration. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:427-432 [Conf ] Jafar Savoj , Ali-Azam Abbasfar , Amir Amirkhany , Bruno W. Garlepp , Mark A. Horowitz A new technique for characterization of digital-to-analog converters in high-speed systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:433-438 [Conf ] Marco Casale-Rossi , Andrzej J. Strojwas , Robert C. Aitken , Antun Domic , Carlo Guardiani , Philippe Magarshack , Douglas Pattullo , Joseph Sawicki DFM/DFY: should you trust the surgeon or the family doctor? [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:439-442 [Conf ] Ajay K. Verma , Paolo Ienne Automatic synthesis of compressor trees: reevaluating large counters. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:443-448 [Conf ] María C. Molina , Rafael Ruiz-Sautua , Jose Manuel Mendias , Román Hermida Area optimization of multi-cycle operators in high-level synthesis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:449-454 [Conf ] Maciej J. Ciesielski , Serkan Askar , D. Gomez-Prado , Jérémie Guillot , Emmanuel Boutillon Data-flow transformations using Taylor expansion diagrams. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:455-460 [Conf ] Yee Jern Chong , Sri Parameswaran Automatic application specific floating-point unit generation. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:461-466 [Conf ] Mario Schölzel Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:467-472 [Conf ] Applications for ubiquitous computing and communications. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:473- [Conf ] Matthias Krause , Oliver Bringmann , André Hergenhan , Gökhan Tabanoglu , Wolfgang Rosenstiel Timing simulation of interconnected AUTOSAR software-components. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:474-479 [Conf ] Sergio Saponara , Esa Petri , Marco Tonarelli , Iacopo Del Corona , Luca Fanucci FPGA-based networking systems for high data-rate and reliable in-vehicle communications. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:480-485 [Conf ] F. D'Ascoli , Francesco Iozzi , Corrado Marino , M. Melani , Marco Tonarelli , Luca Fanucci , A. Giambastiani , A. Rocchi , M. De Marinis Low-g accelerometer fast prototyping for automotive applications. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:486-491 [Conf ] Riccardo Mariani , Gabriele Boschi , Federico Colucci Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:492-497 [Conf ] Christopher Claus , Johannes Zeppenfeld , Florian Helmut Müller , Walter Stechele Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:498-503 [Conf ] Patrick Popp , Marco Di Natale , Paolo Giusto , Sri Kanajan , Claudio Pinello Interactive presentation: Towards a methodology for the quantitative evaluation of automotive architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:504-509 [Conf ] Yu Huang Dynamic learning based scan chain diagnosis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:510-515 [Conf ] Ozgur Sinanoglu , Philip Schremmer Diagnosis, modeling and tolerance of scan chain hold-time violations. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:516-521 [Conf ] Irith Pomeranz , Sudhakar M. Reddy On test generation by input cube avoidance. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:522-527 [Conf ] A. Ney , Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian Slow write driver faults in 65nm SRAM technology: analysis and March test solution. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:528-533 [Conf ] V. R. Devanathan , C. P. Ravikumar , V. Kamakoti Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:534-539 [Conf ] Kunal P. Ganeshpure , Sandip Kundu Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:540-545 [Conf ] Yu Wang , Hong Luo , Ku He , Rong Luo , Huazhong Yang , Yuan Xie Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:546-551 [Conf ] Tao Xu , Krishnendu Chakrabarty A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:552-557 [Conf ] Zeljko Zilic , Katarzyna Radecka , Ali Kazamiphur Reversible circuit technology mapping from non-reversible specifications. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:558-563 [Conf ] Nicholas H. Zamora , Jung-Chun Kao , Radu Marculescu Distributed power-management techniques for wireless network video systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:564-569 [Conf ] Federico Angiolini , M. Haykel Ben Jamaa , David Atienza , Luca Benini , Giovanni De Micheli Interactive presentation: Improving the fault tolerance of nanometric PLA designs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:570-575 [Conf ] Kundan Nepal , R. Iris Bahar , Joseph L. Mundy , William R. Patterson , Alexander Zaslavsky Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:576-581 [Conf ] Seok-Won Seong , Prabhat Mishra An efficient code compression technique using application-aware bitmask and dictionary selection methods. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:582-587 [Conf ] Kubilay Atasu , Robert G. Dimond , Oskar Mencer , Wayne Luk , Can C. Özturan , Günhan Dündar Optimizing instruction-set extensible processors under data bandwidth constraints. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:588-593 [Conf ] Juan Hamers , Lieven Eeckhout Resource prediction for media stream decoding. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:594-599 [Conf ] JongSoo Park , Sung-Boem Park , James D. Balfour , David Black-Schaffer , Christos Kozyrakis , William J. Dally Register pointer architecture for efficient embedded processors. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:600-605 [Conf ] S. van Haastregt , Peter M. W. Knijnenburg Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:606-611 [Conf ] Athanasios Milidonis , N. Alachiotis , V. Porpodas , Haralambos Michail , Athanasios Kakarountas , Constantinos E. Goutis Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:612-617 [Conf ] Nikhil Jayakumar , Sunil P. Khatri An algorithm to minimize leakage through simultaneous input vector control and circuit modification. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:618-623 [Conf ] Meeta S. Gupta , Jarod L. Oatley , Russ Joseph , Gu-Yeon Wei , David M. Brooks Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:624-629 [Conf ] Nilanjan Banerjee , Georgios Karakonstantis , Kaushik Roy Process variation tolerant low power DCT architecture. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:630-635 [Conf ] Yan Lin , Lei He Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:636-641 [Conf ] André C. Nácul , Francesco Regazzoni , Marcello Lajolo Hardware scheduling support in SMP architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:642-647 [Conf ] Tobias Bjerregaard , Mikkel Bystrup Stensgaard , Jens Sparsø A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:648-653 [Conf ] Hazem Moussa , Olivier Muller , Amer Baghdadi , Michel Jézéquel Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:654-659 [Conf ] Simone Medardoni , Martino Ruggiero , Davide Bertozzi , Luca Benini , Giovanni Strano , Carlo Pistritto Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:660-665 [Conf ] Jukka Suhonen , Mikko Kohvakka , Mauri Kuorilehto , Marko Hännikäinen , Timo D. Hämäläinen Cost-aware capacity optimization in dynamic multi-hop WSNs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:666-671 [Conf ] Ingrid Verbauwhede , Patrick Schaumont Design methods for security and trust. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:672-677 [Conf ] Dr Heikki Huomo Emerging solutions technology and business views for the ubiquitous communication. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:678- [Conf ] Louis Baguena , Emmanuel Liégeon , Alexandra Bépoix , Jean-Marc Dusserre , Christophe Oustric , Philippe Bellocq , Vincent Heiries Development of on board, highly flexible, Galileo signal generator ASIC. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:679-683 [Conf ] D. Hairion , S. Emeriau , E. Combot , M. Sarlotte New safety critical radio altimeter for airbus and related design flow. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:684-688 [Conf ] Robert Lissel , Joachim Gerlach , Robert Bosch GmbH Introducing new verification methods into a company's design flow: an industrial user's point of view. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:689-694 [Conf ] Mitchell Lin , Kwang-Ting (Tim) Cheng Testable design for advanced serial-link transceivers. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:695-700 [Conf ] David C. Keezer , Dany Minier , Patrice Ducharme Method for reducing jitter in multi-gigahertz ATE. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:701-706 [Conf ] Jens Anders , Shaji Krishnan , Guido Gronthoud Re-configuration of sub-blocks for effective application of time domain tests. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:707-712 [Conf ] Erdem S. Erdogan , Sule Ozev An ADC-BiST scheme using sequential code analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:713-718 [Conf ] Jerzy Dabrowski , Rashad Ramzan Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:719-724 [Conf ] P. Yeung , A. Torres , P. Batra Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:725-730 [Conf ] J. Tongbong , Salvador Mir , Jean-Louis Carbonéro Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:731-736 [Conf ] I. O'Connor , B. Courtois , K. Chakrabarty , N. Delorme , M. Hampton , J. Hartung Heterogeneous systems on chip and systems in package. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:737-742 [Conf ] Ilya Wagner , Valeria Bertacco Engineering trust with semantic guardians. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:743-748 [Conf ] Dohyung Kim , Soonhoi Ha , Rajesh Gupta CATS: cycle accurate transaction-driven simulation with multiple processor simulators. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:749-754 [Conf ] Ann Gordon-Ross , Pablo Viana , Frank Vahid , Walid A. Najjar , Edna Barros A one-shot configurable-cache tuner for improved energy and performance. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:755-760 [Conf ] Deepak Mathaikutty , Sandeep K. Shukla , Sreekumar V. Kodakara , David J. Lilja , Ajit Dingankar Design fault directed test generation for microprocessor validation. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:761-766 [Conf ] Wolfgang Ecker , Volkan Esen , Lars Schönberg , Thomas Steininger , Michael Velten , Michael Hull Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:767-772 [Conf ] Clemens Moser , Lothar Thiele , Davide Brunelli , Luca Benini Adaptive power management in energy harvesting systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:773-778 [Conf ] Qinru Qiu , Ying Tan , Qing Wu Stochastic modeling and optimization for robust power management in a partially observable system. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:779-784 [Conf ] Po-Kuan Huang , Soheil Ghiasi Efficient and scalable compiler-directed energy optimization for realtime applications. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:785-790 [Conf ] Linwei Niu , Gang Quan Interactive presentation: Peripheral-conscious scheduling on energy minimization for weakly hard real-time systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:791-796 [Conf ] Ryo Watanabe , Masaaki Kondo , Masashi Imai , Hiroshi Nakamura , Takashi Nanya Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:797-802 [Conf ] Andhi Janapsatya , Aleksandar Ignjatovic , Sri Parameswaran , Jörg Henkel Instruction trace compression for rapid instruction cache simulation. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:803-808 [Conf ] Talal Bonny , Jörg Henkel Efficient code density through look-up table compression. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:809-814 [Conf ] Yunsi Fei , Z. Jerry Shi Microarchitectural support for program code integrity monitoring in application-specific instruction set processors. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:815-820 [Conf ] David Sheldon , Frank Vahid , Stefano Lonardi Interactive presentation: Soft-core processor customization using the design of experiments paradigm. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:821-826 [Conf ] Power supply and power management in Ubicom. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:827- [Conf ] M. Brandenburg , A. Schöllhorn , S. Heinen , Josef Eckmueller , T. Eckart From algorithm to first 3.5G call in record time: a novel system design approach based on virtual prototyping and its consequences for interdisciplinary system design teams. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:828-830 [Conf ] Maurizio Paganini , Georg Kimmich , Stephane Ducrey , Guilhem Caubit , Vincent Coeffe Portable multimedia SoC design: a global challenge. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:831-834 [Conf ] Neal Wingen What if you could design tomorrow's system today? [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:835-840 [Conf ] Hamidreza Hashempour , Fabrizio Lombardi Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:841-846 [Conf ] B. Jang , Y-B. Kim , F. Lombardi Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profiling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:847-852 [Conf ] Paul Wielage , Erik Jan Marinissen , Michel Altheimer , Clemens Wouters Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:853-858 [Conf ] Tobias Dubois , Erik Jan Marinissen , Mohamed Azimane , Paul Wielage , Erik Larsson , Clemens Wouters Test quality analysis and improvement for an embedded asynchronous FIFO. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:859-864 [Conf ] Wenjing Rao , Alex Orailoglu , Ramesh Karri Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:865-869 [Conf ] Shan Tang , Qiang Xu A multi-core debug platform for NoC-based systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:870-875 [Conf ] L. Moss , Maxime de Nanclas , Luc Filion , S. Fontaine , Guy Bois , M. Aboulhamid Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:876-881 [Conf ] Nicola Bombieri , Franco Fummi , Graziano Pravadelli Incremental ABV for functional validation of TL-to-RTL design refinement. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:882-887 [Conf ] Ioannis Mavroidis , Ioannis Papaefstathiou Efficient testbench code synthesis for a hardware emulator system. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:888-893 [Conf ] Wolfgang Ecker , Volkan Esen , Thomas Steininger , Michael Velten , Michael Hull Interactive presentation: Implementation of a transaction level assertion framework in SystemC. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:894-899 [Conf ] Shireesh Verma , Ian G. Harris , Kiran Ramineni Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:900-905 [Conf ] Kai Chen 0003 , Janos Sztipanovits , Sandeep Neema Compositional specification of behavioral semantics. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:906-911 [Conf ] Kai Huang , Lothar Thiele Performance analysis of multimedia applications using correlated streams. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:912-917 [Conf ] Vojtech Derbek , Christian Steger , Reinhold Weiss , Daniel Wischounig , Josef Preishuber-Pfluegl , Markus Pistauer Simulation platform for UHF RFID. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:918-923 [Conf ] Andreas Bauer 0002 , Markus Pister , Michael Tautschnig Tool-support for the analysis of hybrid systems and models. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:924-929 [Conf ] Thomas Huining Feng , Lynn Wang , Wei Zheng , Sri Kanajan , Sanjit A. Seshia Interactive presentation: Automatic model generation for black box real-time systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:930-935 [Conf ] Reimund Wittmann , Massimo Vanzi , Hans-Joachim Wassener , Navraj Nandra , Joachim Kunkel , Jose Franca , Christian Münker Life begins at 65: unless you are mixed signal? [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:936-941 [Conf ] Evgeny Bolotin , Israel Cidon , Ran Ginosar , Avinoam Kolodny Routing table minimization for irregular mesh NoCs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:942-947 [Conf ] J. W. van den Brand , Calin Ciordas , Kees Goossens , Twan Basten Congestion-controlled best-effort communication for networks-on-chip. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:948-953 [Conf ] Andreas Hansson , Martijn Coenen , Kees Goossens Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:954-959 [Conf ] Rajesh Galivanche , Rohit Kapur , Antonio Rubio Testing in the year 2020. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:960-965 [Conf ] Grégory Gailliard , Eric Nicollet , Michel Sarlotte , François Verdier Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:966-971 [Conf ] Ingemar Söderquist Event driven data processing architecture. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:972-976 [Conf ] Björn Fiethe , H. Michalik , C. Dierker , B. Osterloh , G. Zhou Reconfigurable system-on-chip data processing units for space imaging instruments. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:977-982 [Conf ] B. Rousseau , Philippe Manet , D. Galerin , D. Merkenbreack , Jean-Didier Legat , F. Dedeken , Yves Gabriel Enabling certification for dynamic partial reconfiguration using a minimal flow. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:983-988 [Conf ] Julie Ferrigno , Philippe Perdu , Kevin Sanchez , Dean Lewis Identification of process/design issues during 0.18 µm technology qualification for space application. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:989-993 [Conf ] Philippe Manet , Daniel Maufroid , Leonardo Tosi , Marco Di Ciano , Olivier Mulertt , Yves Gabriel , Jean-Didier Legat , Denis Aulagnier , Christian Gamrat , Raffaele Liberati , Vincenzo La Barba Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:994-999 [Conf ] Saurabh K. Tiwary , Joel R. Phillips WAVSTAN: waveform based variational static timing analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1000-1005 [Conf ] Shweta Srivastava , Jaijeet S. Roychowdhury Rapid and accurate latch characterization via direct Newton solution of setup/hold times. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1006-1011 [Conf ] B. Lasbouygues , Robin Wilson , Nadine Azémard , Philippe Maurine Temperature and voltage aware timing analysis: application to voltage drops. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1012-1017 [Conf ] D. Tadesse , D. Sheffield , E. Lenge , R. Iris Bahar , Joel Grodstein Accurate timing analysis using SAT and pattern-dependent delay models. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1018-1023 [Conf ] Egor R. V. Bondarev , Michel Chaudron , Peter H. N. de With CARAT: a toolkit for design and performance analysis of component-based embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1024-1029 [Conf ] E. Alessio , Franco Fummi , Davide Quaglia , Maura Turolla Modeling and simulation alternatives for the design of networked embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1030-1035 [Conf ] Stylianos Mamagkakis , Dimitrios Soudris , Francky Catthoor Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1036-1041 [Conf ] Felix Jesús Villanueva , David Villa , Francisco Moya , Jesús Barba , Fernando Rincón , Juan Carlos López Lightweight middleware for seamless HW-SW interoperability, with application to wireless sensor networks. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1042-1047 [Conf ] Franco Fummi , Giovanni Perbellini , R. Pietrangeli , Davide Quaglia Interactive presentation: A middleware-centric design flow for networked embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1048-1053 [Conf ] Ani Nahapetian , Paolo Lombardo , Andrea Acquaviva , Luca Benini , Majid Sarrafzadeh Dynamic reconfiguration in sensor networks with regenerative energy sources. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1054-1059 [Conf ] Hwisung Jung , Massoud Pedram Dynamic power management under uncertain information. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1060-1065 [Conf ] Praveen Raghavan , Andy Lambrechts , Murali Jayapala , Francky Catthoor , Diederik Verkest , Henk Corporaal Very wide register: an asymmetric register file organization for low power embedded processors. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1066-1071 [Conf ] Mihir R. Choudhury , Kyle Ringgenberg , Scott Rixner , Kartik Mohanram Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1072-1077 [Conf ] Pietro Babighian , Gila Kamhi , Moshe Y. Vardi Interactive presentation: PowerQuest: trace driven data mining for power optimization. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1078-1083 [Conf ] Matthieu Briere , Bruno Girodias , Youcef Bouchebaba , Gabriela Nicolescu , Fabien Mieyeville , Frédéric Gaffiot , Ian O'Connor System level assessment of an optical NoC in an MPSoC platform. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1084-1089 [Conf ] A. Sheibanyrad , Ivan Miro Panades , Alain Greiner Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1090-1095 [Conf ] Ümit Y. Ogras , Radu Marculescu Analytical router modeling for networks-on-chip performance analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1096-1101 [Conf ] Christian Sauer , Matthias Gries , Sebastian Dirk Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1102-1107 [Conf ] Thierry Pardessus , Heinrich Daembkes , Richard Arning The methodological and technological dimensions of technology transfer for embedded systems in aeronautics and space. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1108-1109 [Conf ] Johann Großschädl , Stefan Tillich , Christian Rechberger , Michael Hofmann , Marcel Medwed Energy evaluation of software implementations of block ciphers under memory constraints. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1110-1115 [Conf ] Monjur Alam , Sonai Ray , Debdeep Mukhopadhyay , Santosh Ghosh , Dipanwita Roy Chowdhury , Indranil Sengupta An area optimized reconfigurable encryptor for AES-Rijndael. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1116-1121 [Conf ] S. H. K. Narayanan , Mahmut T. Kandemir , R. Brooks Performance aware secure code partitioning. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1122-1127 [Conf ] Najwa Aaraj , Anand Raghunathan , Srivaths Ravi , Niraj K. Jha Energy and execution time analysis of a software-based trusted platform module. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1128-1133 [Conf ] Luong Dinh Hung , Hidetsugu Irie , Masahiro Goshima , Shuichi Sakai Utilization of SECDED for soft error and variation-induced defect tolerance in caches. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1134-1139 [Conf ] Satish Narayanasamy , Ayse Kivilcim Coskun , Brad Calder Transient fault prediction based on anomalies in processor events. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1140-1145 [Conf ] Mojtaba Mehrara , Mona Attariyan , Smitha Shyam , Kypros Constantinides , Valeria Bertacco , Todd M. Austin Low-cost protection for SER upsets and silicon defects. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1146-1151 [Conf ] Madhu Mutyam , Narayanan Vijaykrishnan Working with process variation aware caches. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1152-1157 [Conf ] Ernesto Sánchez , Massimiliano Schillaci , Giovanni Squillero , Matteo Sonza Reorda Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1158-1163 [Conf ] Qiang Zhu , Aviral Shrivastava , Nikil Dutt Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1164-1169 [Conf ] In-Ho Moon , Per Bjesse , Carl Pixley A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1170-1175 [Conf ] Daniel Große , Ulrich Kühne , Rolf Drechsler Estimating functional coverage in bounded model checking. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1176-1181 [Conf ] Sean Safarpour , Andreas G. Veneris Abstraction and refinement techniques in automated design debugging. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1182-1187 [Conf ] Roderick Bloem , Stefan Galler , Barbara Jobstmann , Nir Piterman , Amir Pnueli , Martin Weiglhofer Interactive presentation: Automatic hardware synthesis from specifications: a case study. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1188-1193 [Conf ] Tarek Moselhy , Xin Hu , Luca Daniel pFFT in FastMaxwell: a fast impedance extraction solver for 3D conductor structures over substrate. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1194-1199 [Conf ] Xin Hu , Tarek Moselhy , Jacob K. White , Luca Daniel Optimization-based wideband basis functions for efficient interconnect extraction. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1200-1205 [Conf ] Mosin Mondal , Andrew J. Ricketts , Sami Kirolos , Tamer Ragheb , Greg M. Link , Narayanan Vijaykrishnan , Yehia Massoud Thermally robust clocking schemes for 3D integrated circuits. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1206-1211 [Conf ] Tsai-Ying Lin , Tsung-Han Lin , Hui-Hsiang Tung , Rung-Bin Lin Double-via-driven standard cell library design. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1212-1217 [Conf ] Jingye Xu , Abinash Roy , Masud H. Chowdhury Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1218-1223 [Conf ] Laura Pozzi , Pierre G. Paulin A future of customizable processors: are we there yet? [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1224-1225 [Conf ] Peter Spindler , Frank M. Johannes Fast and accurate routing demand estimation for efficient routability-driven placement. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1226-1231 [Conf ] Paolo Azzoni , Massimo Bertoletti , Nicola Dragone , Franco Fummi , Carlo Guardiani , W. Vendraminetto Yield-aware placement optimization. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1232-1237 [Conf ] Hushrav Mogal , Kia Bazargan Microarchitecture floorplanning for sub-threshold leakage reduction. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1238-1243 [Conf ] Xavier Olive , Jean-Marie Pasquet , Didier Flament Industrial applications. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1244-1245 [Conf ] Jean Botti Flying embedded: the industrial scene and challenges for embedded systems in aeronautics and space. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1246- [Conf ] Timo Alho , Panu Hämäläinen , Marko Hännikäinen , Timo D. Hämäläinen Compact hardware design of Whirlpool hashing core. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1247-1252 [Conf ] Steffen Peter , Peter Langendörfer , Krzysztof Piotrowski Flexible hardware reduction for elliptic curve cryptography in GF(2m ). [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1259-1264 [Conf ] Kuan Jen Lin , Shan Chien Fang , Shih Hsien Yang , Cheng Chia Lo Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1265-1270 [Conf ] José Luis Rosselló , Carol de Benito , Sebastià A. Bota , Jaume Segura Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1271-1276 [Conf ] Tejasvi Das , P. R. Mukund Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1277-1282 [Conf ] Dongwoo Hong , Shadi Saberi , Kwang-Ting Cheng , C. Patrick Yue A two-tone test method for continuous-time adaptive equalizers. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1283-1288 [Conf ] Robert Aitken , Sachin Idgunji Worst-case design and margin for embedded SRAM. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1289-1294 [Conf ] Michele Favalli , Cecilia Metra Interactive presentation: Pulse propagation for the detection of small delay defects. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1295-1300 [Conf ] Amir Zjajo , Manuel J. Barragan Asian , José Pineda de Gyvez Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1301-1306 [Conf ] Lei Fang , Michael S. Hsiao A new hybrid solution to boost SAT solver performance. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1307-1313 [Conf ] Chi-An Wu , Ting-Hao Lin , Chih-Chun Lee , Chung-Yang Huang QuteSAT: a robust circuit-based SAT solver for complex circuit structure. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1313-1318 [Conf ] Gianpiero Cabodi , Sergio Nocco , Stefano Quer Boosting the role of inductive invariants in model checking. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1319-1324 [Conf ] Daniel Kroening , Natasha Sharygina Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1325-1330 [Conf ] Paolo Bonzini , Laura Pozzi Polynomial-time subgraph enumeration for automated instruction set extension. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1331-1336 [Conf ] Mehrdad Reshadi , Daniel Gajski Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1337-1342 [Conf ] Zhiguo Ge , Weng-Fai Wong , Hock-Beng Lim DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1343-1348 [Conf ] Stefan Kraemer , Rainer Leupers , Gerd Ascheid , Heinrich Meyr Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1349-1354 [Conf ] Sjoerd Meijer , Bart Kienhuis , Alexandru Turjan , Erwin A. de Kock Interactive presentation: A process splitting transformation for Kahn process networks. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1355-1360 [Conf ] Suwen Yang , Mark R. Greenstreet Computing synchronizer failure probabilities. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1361-1366 [Conf ] David Bañeres , Jordi Cortadella , Michael Kishinevsky Layout-aware gate duplication and buffer insertion. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1367-1372 [Conf ] Min Ni , Seda Ogrenci Memik Self-heating-aware optimal wire sizing under Elmore delay model. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1373-1378 [Conf ] Amith Singhee , Rob A. Rutenbar Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1379-1384 [Conf ] Yi Feng , Zheng Zhou , Dong Tong , Xu Cheng Clock domain crossing fault model and coverage metric for validation of SoC design. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1385-1390 [Conf ] Min Chen , Wei Zhao , Frank Liu , Yu Cao Fast statistical circuit analysis with finite-point based transistor model. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1391-1396 [Conf ] W. Schneider , M. Schroter , W. Kraus , H. Wittkopf Interactive presentation: Statistical simulation of high-frequency bipolar circuits. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1397-1402 [Conf ] Michel Riffiod , Paul Caspi , Christophe Piala , Jean-Luc Voirin Development and industrialisation. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1403-1405 [Conf ] M. Schämann , S. Hessel , U. Langmann , M. Bücker Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1406-1411 [Conf ] Cyprian Grassmann , Mathias Richter , Mirko Sauermann Mapping the physical layer of radio standards to multiprocessor architectures. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1412-1417 [Conf ] K. Van Renterghem , P. Demuytere , Dieter Verhulst , Jan Vandewege , Xing-Zhi Qiu Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1418-1423 [Conf ] Marco Crepaldi , Mario R. Casu , Mariagrazia Graziano , Maurizio Zamboni An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1424-1429 [Conf ] E. Barajas , R. Cosculluela , D. Coutinho , D. Mateo , J. L. González , I. Cairò , S. Banda , M. Ikeda Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1430-1435 [Conf ] Natasa Miskov-Zivanov , Diana Marculescu Soft error rate analysis for sequential circuits. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1436-1441 [Conf ] Sanjit A. Seshia , Wenchao Li , Subhasish Mitra Verification-guided soft error resilience. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1442-1447 [Conf ] E. L. Rhod , C. A. Lisboa , Luigi Carro A low-SER efficient core processor architecture for future technologies. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1448-1453 [Conf ] Mihir R. Choudhury , Kartik Mohanram Accurate and scalable reliability analysis of logic circuits. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1454-1459 [Conf ] Balkaran S. Gill , Christos A. Papachristou , Francis G. Wolff Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1460-1465 [Conf ] Andrew B. Kahng Design challenges at 65nm and beyond. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1466-1467 [Conf ] Hermann Kopetz The ARTEMIS cross-domain architecture for embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1468-1469 [Conf ] Ahmed Amine Jerraya HW/SW implementation from abstract architecture models. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1470-1471 [Conf ] Huynh Phung Huynh , Tulika Mitra Instruction-set customization for real-time embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1472-1477 [Conf ] Soyoung Park , Hae-woo Park , Soonhoi Ha A novel technique to use scratch-pad memory for stack management. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1478-1483 [Conf ] Isabelle Puaut , Christophe Pais Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1484-1489 [Conf ] Makoto Sugihara , Tohru Ishihara , Kazuaki Murakami Task scheduling for reliable cache architectures of multiprocessor systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1490-1495 [Conf ] Ngai Wong Fast positive-real balanced truncation of symmetric systems using cross Riccati equations. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1496-1501 [Conf ] Zhenhai Zhu , Joel R. Phillips Random sampling of moment graph: a stochastic Krylov-reduction algorithm. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1502-1507 [Conf ] Jeffrey Fan , Ning Mi , Sheldon X.-D. Tan , Yici Cai , Xianlong Hong Statistical model order reduction for interconnect circuits considering spatial correlations. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1508-1513 [Conf ] Hengliang Zhu , Xuan Zeng , Wei Cai , Jintao Xue , Dian Zhou A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1514-1519 [Conf ] Stephane Bronckers , Charlotte Soens , Geert Van der Plas , Gerd Vandersteen , Yves Rolain Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1520-1525 [Conf ] Yongpan Liu , Robert P. Dick , Li Shang , Huazhong Yang Accurate temperature-dependent integrated circuit leakage power estimation is easy. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1526-1531 [Conf ] Swaroop Ghosh , Swarup Bhunia , Kaushik Roy Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1532-1537 [Conf ] Hratch Mangassarian , Andreas G. Veneris , Sean Safarpour , Farid N. Najm , Magdy S. Abadir Maximum circuit activity estimation using pseudo-boolean satisfiability. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1538-1543 [Conf ] A. Sathanur , Andrea Calimera , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1544-1549 [Conf ] Myeong-Eun Hwang , Tamer Cakici , Kaushik Roy Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1550-1555 [Conf ] Peggy Aycinena , Eric Bantegnie , Gerard Ladier , Ralph Mueller , Franco Gasperoni , Alex Wilson Towards total open source in aeronautics and space? [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1556- [Conf ] Pawel Gburzynski , Bozena Kaminska , Wladek Olesinski A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1557-1562 [Conf ] Gummidipudi Krishnaiah , Nur Engin , Sergei Sawitzki Scalable reconfigurable channel decoder architecture for future wireless handsets. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1563-1568 [Conf ] Zahid Khan , Tughrul Arslan , John S. Thompson , Ahmet T. Erdogan A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1569-1574 [Conf ] Afxendios Tychopoulos , Odysseas G. Koufopavlou Optimization of the "FOCUS" Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channels. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1575-1580 [Conf ] Sung-Jui (Song-Ra) Pan , Kwang-Ting Cheng A framework for system reliability analysis considering both system error tolerance and component test quality. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1581-1586 [Conf ] Régis Leveugle , Abdelaziz Ammari , V. Maingot , E. Teyssou , Pascal Moitrel , Christophe Mourtel , Nathalie Feyt , Jean-Baptiste Rigaud , Assia Tria Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1587-1592 [Conf ] Benoît Godard , Jean Michel Daga , Lionel Torres , Gilles Sassatelli Evaluation of design for reliability techniques in embedded flash memories. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1593-1598 [Conf ] Tong-Yu Hsieh , Kuen-Jong Lee , Melvin A. Breuer Reduction of detected acceptable faults for yield improvement via error-tolerance. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1599-1604 [Conf ] A. Nardi , Emre Tuncer , S. Naidu , A. Antonau , S. Gradinaru , Tao Lin , J. Song Use of statistical timing analysis on real designs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1605-1610 [Conf ] Feng Wang 0004 , Yuan Xie , Hai Ju A novel criticality computation method in statistical timing analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1611-1616 [Conf ] Luís Guerra e Silva , Luis Miguel Silveira , Joel R. Phillips Efficient computation of the worst-delay corner. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1617-1622 [Conf ] Lei Ju , Samarjit Chakraborty , Abhik Roychoudhury Accounting for cache-related preemption delay in dynamic priority schedulability analysis. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1623-1628 [Conf ] Jian-Jia Chen , Tei-Wei Kuo , Chia-Lin Yang , Ku-Jei King Energy-efficient real-time task scheduling with task rejection. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1629-1634 [Conf ] Liliana Cucu , Joël Goossens Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1635-1640 [Conf ] Meikang Qiu , Chun Xue , Zili Shao , Edwin Hsing-Mean Sha Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1641-1646 [Conf ] Alireza Ejlali , Bashir M. Al-Hashimi , Paul M. Rosinger , Seyed Ghassem Miremadi Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1647-1652 [Conf ] Eric Humenay , David Tarjan , Kevin Skadron Impact of process variations on multicore performance symmetry. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1653-1658 [Conf ] Ayse Kivilcim Coskun , Tajana Simunic Rosing , Keith Whisnant Temperature aware task scheduling in MPSoCs. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1659-1664 [Conf ] Olga Golubeva , Mirko Loghi , Massimo Poncino , Enrico Macii Architectural leakage-aware management of partitioned scratchpad memories. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1665-1670 [Conf ] Mahmut T. Kandemir , Taylan Yemliha , Seung Woo Son , Ozcan Ozturk Memory bank aware dynamic loop scheduling. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1671-1676 [Conf ] Saif Ali Butt , Stefan Schmermbeck , Jurij Rosenthal , Alexander Pratsch , Eike Schmidt System level clock tree synthesis for power optimization. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1677-1682 [Conf ]