Conferences in DBLP
Ignacio Bravo , Pedro Jiménez , Manuel Mazo , José Luis Lázaro , Alfredo Gardel Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Volcan Agostini , Sergio Bampi FPGA Based Architectures for H. 264/AVC Video Compression Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Volcan Agostini , Arnaldo Azevedo , Vagner S. Rosa , Eduardo A. Berriel , Tatiana G. S. dos Santos , Sergio Bampi , Altamiro Amadeu Susin FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Morra , M. Sackmann , Sunil Shukla , Jürgen Becker , Reiner W. Hartenstein From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Valavan Manohararajah , Stephen Dean Brown , Zvonko G. Vranesic Adaptive FPGAs: High-Level Architecture and a Synthesis Method. [Citation Graph (0, 0)][DBLP ] Conf ] David Grant , Scott Chin , Guy G. Lemieux Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Kieron Turkington , Konstantinos Masselos , George A. Constantinides , Philip Leong FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Elias Todorovich , Eduardo I. Boemo A-B Nodes Classification for Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Taher , Tarek A. El-Ghazawi A Segmentation Model for Partial Run-Time Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Thilo Streichert Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Alfke Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Su-Shin Ang , George A. Constantinides Dynamic Memory Sub-System for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Christos-Savvas Bouganis , Peter Y. K. Cheung , Li Zhaoping FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten Bieser A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment. [Citation Graph (0, 0)][DBLP ] Conf ] Joachim Becker , Yiannos Manoli Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Lejla Batina , Alireza Hodjat , David Hwang , Kazuo Sakiyama , Ingrid Verbauwhede Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Luis G. Barbero , John S. Thompson FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nastaran Baradaran , Pedro C. Diniz Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Sajid Baloch , Tughrul Arslan , Adrian Stoica An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Zachary K. Baker , Viktor K. Prasanna , Hong-Jip Jung Regular Expression Software Deceleration for Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sutjipto Arifin , Peter Y. K. Cheung Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Schallenberg , Wolfgang Nebel , Frank Oppenheimer OSSS+R: Modelling and Simulating Self-Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Leandro Möller , Ismael Grehs , Ney Calazans , Fernando Moraes Reconfigurable Systems Enabled by a Network-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Pil Woo Chun , Lev Kirischian A Framework for a Dynamically Reconfigurable System in a Parallel Multi-Tasking Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Zhi Guo , Abhishek Mitra , Walid A. Najjar Automation of IP Core Interface Generation for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Van Court , Martin C. Herbordt Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique. [Citation Graph (0, 0)][DBLP ] Conf ] F. J. Toledo , J. J. Martinez , J. Garrigos , J. Ferrandez , V. Rodellar Skin Color Detection for Real Time Mobile Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Cao Zhang , Duncan A. Buell , Allen Michalski The Darpa Multiple Precision Arithmetic Benchmark on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaud Lagger , Andres Upegui , Eduardo Sanchez , Ivan Gonzalez Self-Reconfigurable Pervasive Platform for Cryptographic Application. [Citation Graph (0, 0)][DBLP ] Conf ] Christoforos Kachris , Stamatis Vassiliadis A Dynamically Reconfigurable Queue Scheduler. [Citation Graph (0, 0)][DBLP ] Conf ] Allan Carroll , Carl Ebeling Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] F. Rivera , Marcos Sanchez-Elez , Milagros Fernández , Román Hermida , Nader Bagherzadeh Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Dionisios N. Pnevmatikatos , Aggelos Arelakis Variable-Length Hashing for Exact Pattern Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Ken McElvain FPGAs at 65NM and Beyond - Powerful New FPGAs Bring New Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] David B. Thomas , Wayne Luk Non-Uniform Random Number Generation Through Piecewise Linear Approximations. [Citation Graph (0, 0)][DBLP ] Conf ] Mariano Lopez Garcia , Enrique F. Canto Navarro FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Julien Lamoureux , Steven J. E. Wilton Activity Estimation for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Balasubramanian Sethuraman Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Maria Carmen Perez , Jesús Ureña , Álvaro Hernández , Carlos De Marziani , A. Ochoa , William P. Marnane FPGA Implementation of an Efficient Correlator for Complementary Sets of Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Mário P. Véstias , Horácio C. Neto A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Allen Michalski , Duncan A. Buell A Scalable Architecture for RSA Cryptography on Large FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Mustafa Gök , Çaglar Yilmaz Efficient Cell Designs for Systolic Smith-Waterman Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] E. Perez Ramo , Javier Resano A Dual Cache for Performance and Energy Aware Reconfigurable HW. [Citation Graph (0, 0)][DBLP ] Conf ] K. Kobayashi , Manabu Kotani , Kazuya Katsuki , Y. Takatsukasa , K. Ogata , Y. Sugihara , Hidetoshi Onodera A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Torben Weinkopf , Klaus Harbich , Erich Barke Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Brenner , Jan van der Veen , Sándor P. Fekete , J. Oliveira Filho , Wolfgang Rosenstiel Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yana Esteves Krasteva , Eduardo de la Torre , Teresa Riesgo , Didier Joly Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Christos A. Papachristou , J. Weaver , R. Vijayakumar , Francis G. Wolff A Dynamic Reconfigurable Fabric for Platform SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Oppold Evaluation and Design of Processor-Like Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Noori , Farhad Mehdipour , Kazuaki Murakami , Koji Inoue , Morteza Saheb Zamani A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Kentaro Nakahara , Shin'ichi Kouyama , Tomonori Izumi , Hiroyuki Ochi , Yukihiro Nakamura Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells. [Citation Graph (0, 0)][DBLP ] Conf ] María José Moure , María Dolores Valdés , Pablo Rodiz , Loreto Rodríguez-Pardo , José Fariña An FPGA-Based System on Chip for the Measurement of QCM Sensors Resolution. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Morra Configware Design Space Exploration Using Rewriting Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Somsubhra Mondal , Seda Ogrenci Memik , Nikolaos Bellas Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Miwa Miyata , Hideyuki Tsuchiya , Yuichiro Shibata , Kiyoshi Oguri An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Goncalo M. de Matos , Horácio C. Neto On Reconfigurable Architectures for Efficient Matrix Inversion. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando Pardo , P. López , Diego Cabello , M. Balsi FPGA Implementation of 3-D Thermal Model Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Pearson , Mokhtar Nibouche , Anthony G. Pipe , Chris Melhuish , Ian Gilhespy , Benjamin Mitchinson , Kevin N. Gurney , Tony J. Prescott , Peter Redgrave A Biologically Inspired FPGA Based Implementation of a Tactile Sensory System for Object Recognition and Texture Discrimination. [Citation Graph (0, 0)][DBLP ] Conf ] Cesar Torres-Huitzil Area-Efficient Implementation of a Pulse-Mode Neuron Model. [Citation Graph (0, 0)][DBLP ] Conf ] K. S. Tham , Douglas L. Maskell Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Evangelos F. Stefatos , Tughrul Arslan , Didier Keymeulen , Ian Ferguson Integrating the Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an Evolvable Hardware Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Vinay Sriram , David Kearney High Speed High Fidelity Infrared Scene Simulation Using Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Alastair M. Smith , George A. Constantinides , Peter Y. K. Cheung A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. [Citation Graph (0, 0)][DBLP ] Conf ] Balasubramanian Sethuraman , Ranga Vemuri Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Luis F. Rodriguez-Ramos , Angel Alonso , Fernando Gago , Jose V. Gigante , Guillermo Herrera , Teodora Viera Adaptive Optics Real-Time Control Using FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Huang-Chun Roan , Wen-Jyi Hwang , Chia-Tien Dan Lo Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Thilo Pionteck , Roman Koch , Carsten Albrecht Applying Partial Reconfiguration to Networks-On-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Konstantinos Masselos , George A. Constantinides , Qiang Liu Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo Martinez , Jesus Marin , Carlos Willmott FPGA Based Imaging Particle Detector Trigger System. [Citation Graph (0, 0)][DBLP ] Conf ] Usama Malik , Oliver Diessel The Entropy of FPGA Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gilroy , James Irvine RAID 6 Hardware Acceleration. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Fidjeland , Wayne Luk Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] George Ferizis , Hossam A. ElGindy Mapping Recursive Functions to Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Suhaib A. Fahmy Investigating Trace Transform Architectures for Face Authentication. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro C. Diniz , Gokul Govindu Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit. [Citation Graph (0, 0)][DBLP ] Conf ] G. Adam Covington , Charles L. G. Comstock , Andrew A. Levine , John W. Lockwood , Young H. Cho High Speed Document Clustering in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Van Court , Martin C. Herbordt Sizing of Processing Arrays for FPGA-Based Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan A. Clarke , George A. Constantinides High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] S. Chandrasekaran , A. Amira Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling. [Citation Graph (0, 0)][DBLP ] Conf ] Angel Fernandez Herrero , Alberto Jimenez-Pacheco , Gabriel Caffarena , Javier Casajús-Quirós Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Yohei Hori , Hiroyuki Yokoyama , Kenji Toda Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Mateusz Majer An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization. [Citation Graph (0, 0)][DBLP ] Conf ] Ari Kulmala , Timo D. Hämäläinen , Marko Hännikäinen Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Chidamber Kulkarni , Gordon J. Brebner Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Toshihiro Katashita , Atusi Maeda , Kenji Toda , Yoshinori Yamaguchi A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Heikki Kariniemi , Jari Nurmi On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiyuki Kaeriyama , Daichi Zaitsu , Kazuhiko Komatsu , Ken-ichi Suzuki , Tadao Nakamura , Nobuyuki Ohba Ray Tracing Hardware System Using Plane-Sphere Intersections. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Hutton , Yan Lin , Lei He Placement and Timing for FPGAs Considering Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Pao-Ann Hsiung , Chun-Hsian Huang , Chih-Feng Liao Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Lee W. Howes , Paul Price , Oskar Mencer , Olav Beckmann , Oliver Pell Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description. [Citation Graph (0, 0)][DBLP ] Conf ] S. Chandrasekaran , A. Amira FPGA Implementation and Power Modelling of the Fast Walsh Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco-Javier Veredas , Hans-Jörg Pfleiderer Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Guillermo Marcus Martinez , Gerhard Lienhart , Andreas Kugel , Reinhard Männer On Buffer Management Strategies for High Performance Computing with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriel Caffarena , Juan A. López , Carlos Carreras , Octavio Nieto-Taladriz High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Terrence S. T. Mak , N. Pete Sedcole , Peter Y. K. Cheung , Wayne Luk On-FPGA Communication Architectures and Design Factors. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip H. Jones , John W. Lockwood , Young H. Cho A Thermal Management and Profiling Method for Reconfigurable Hardware Applications. [Citation Graph (0, 0)][DBLP ] Conf ] James Moscola , Young H. Cho , John W. Lockwood Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Martínez , Leonardo Maria Reyneri , Francisco J. Pelayo , Christian A. Morillas , Samuel F. Romero A Codesign Tool for High Level Systhesis of Vision Models on FPL. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Lau , Orion Pritchard Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions. [Citation Graph (0, 0)][DBLP ] Conf ] C. K. Wong , Philip Heng Wai Leong An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Tomotaka Miyashiro , Akira Kitamura , Hironori Nakajo , Noboru Tanabe DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. [Citation Graph (0, 0)][DBLP ] Conf ] Antonin Hermanek , Michal Kunes , Michal Kvasnicka Using Reconfigurable HW for High Dimensional CAF Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Kyprianos Papademetriou , Apostolos Dollas Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Florian Stock , Andreas Koch Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Zhi Guo , Walid A. Najjar A Compiler Intermediate Representation for Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Nele Mentens , Kazuo Sakiyama , Lejla Batina , Ingrid Verbauwhede , Bart Preneel Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Dang Ba Khac Trieu , Tsutomu Maruyama Implementation of a Parallel and Pipelined Watershed Algorithm on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Kostas Siozios , Dimitrios Soudris Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Chin Mun Wee , Peter R. Sutton , Neil W. Bergmann , John A. Williams Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Abdelelah Naoulou , Jean-Louis Boizard , Jean Yves Fourniols , Michel Devy An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Wang , Tapani Ahonen , Jari Nurmi Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Y. L. Chin , Clarence S. P. Lee , Steven J. E. Wilton Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Marco D. Santambrogio , Donatella Sciuto Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Ginés Doménech-Asensi , Juan Martínez-Alajarín , Ramón Ruiz Merino , José-Alejandro López Alcantud Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. [Citation Graph (0, 0)][DBLP ] Conf ] Kenji Kanazawa , Tsutomu Maruyama An FPGA Solver for Large SAT Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Mesquita , Benoît Badrignans , Lionel Torres , Gilles Sassatelli , Michel Robert , Jean-Claude Bajard , Fernando Gehm Moraes A Leak Resistant Architecture Against Side Channel Attacks. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Novotný , Jan Schmidt General Digit Width Normal Basis Multipliers with Circular and Linear Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Page Academia to IPO - A Modern Odyssey. [Citation Graph (0, 0)][DBLP ] Conf ] Jason D. Bakos , Charles L. Cathey , Allen Michalski Predictive Load Balancing for Interconnected FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Pell , Wayne Luk Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information. [Citation Graph (0, 0)][DBLP ] Conf ] Boris Kettelhoit , Mario Porrmann A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ling Zhuo , Viktor K. Prasanna High-Performance and Parameterized Matrix Factorization on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Hayden Kwok-Hay So , Robert W. Brodersen Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support. [Citation Graph (0, 0)][DBLP ] Conf ] Pengyuan Yu , Patrick Schaumont Executing Hardware as Parallel Software for Picoblaze Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Saegusa , Tsutomu Maruyama An FPGA Implementation of K-Means Clustering for Color Images Based on Kd-Tree. [Citation Graph (0, 0)][DBLP ] Conf ] Suhaib A. Fahmy , Christos-Savvas Bouganis , Peter Y. K. Cheung , Wayne Luk Efficient Realtime FPGA Implementation of the Trace Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Yue Zhuo , Hao Li , Saraju P. Mohanty A Congestion Driven Placement Algorithm for FPGA Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Yohei Hasegawa , Shohei Abe , K. Ishikawa , Shunsuke Tsutsumi , Shunsuke Kurotaki , T. Nakamura , T. Nishimura A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] François-Xavier Standaert , Gaël Rouvroy , Jean-Jacques Quisquater FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks. [Citation Graph (0, 0)][DBLP ] Conf ] Sujan Pandey , Manfred Glesner Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Lodi , Claudio Mucci , Massimo Bocchi , Andrea Cappelli , Mario de Dominicis , Luca Ciccarelli A Multi-Context Pipelined Array for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Julio C. Sosa , Rocio Gomez-Fabela , Jose Antonio Boluda , Fernando Pardo FPGA Implementation of a Change-Driven Image Processing Architecture for Optical Flow Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Sims , James Irvine An FPGA Implementation of Pattern-Selective Pyramidal Image Fusion. [Citation Graph (0, 0)][DBLP ] Conf ] Heiko Hinkelmann , Andreas Gunberg , Peter Zipf , Leandro Soares Indrusiak , Manfred Glesner Multitasking Support for Dynamically Reconfig Urable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Julien Lamoureux , Steven J. E. Wilton Architecture and CAD for FPGA Clock Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Wenyin Fu , Katherine Compton A Simulation Platform for Reconfigurable Computing Research. [Citation Graph (0, 0)][DBLP ] Conf ] Ben Cope Can Graphics Processing Units be Used to Improve Video Processing Systems? [Citation Graph (0, 0)][DBLP ] Conf ] Keith Gowan , Jason Nery , Henrick Han , Tony Sheng , Howard Li , Fakhreddine Karray , Insop Song Intelligent Parking System Design Using FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Eslami Dehkordi , Stephen Dean Brown , Terry Borer Modular Partitioning for Incremental Compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Encarnación Castillo , Luis Parrilla , Antonio García , Antonio Lloris , Uwe Meyer-Bäse IPP Watermarking Technique for IP Core Protection on FPL Devices. [Citation Graph (0, 0)][DBLP ] Conf ] David de Andrés , Juan Carlos Ruiz , Daniel Gil , Pedro Gil Fast Emulation of Permanent Faults in VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Enrique Soto , Elena Lago , Juan J. Rodríguez-Andina FPGA Implementation of High-Performance PHM / DPHM Schedulers. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael A. Arce-Nazario , Manuel Jimenez , Domingo Rodriguez High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Beauchamp , Scott Hauck , Keith D. Underwood , K. Scott Hemmert Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Piotr Stepien , Milan Vasilko On Feasibility of FPGA Bitstream Compression During Placement and Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Perschke A Flexible Implementation of a Temporal Filter with Motion Compensation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Ziener , Stefan Assmus , Jürgen Teich Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] K. Van Renterghem , Dieter Verhulst , S. Verschuere , P. Demuytere , Jan Vandewege , Xing-Zhi Qiu A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access. [Citation Graph (0, 0)][DBLP ] Conf ] Lerong Cheng , Jinjun Xiong , Lei He , Mike Hutton FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Michael T. Frederick , Arun K. Somani Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Owen Callanan , David Gregg , Andy Nisbet , Mike Peardon High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD. [Citation Graph (0, 0)][DBLP ] Conf ] Oswaldo Cadenas , Graham M. Megson Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor. [Citation Graph (0, 0)][DBLP ] Conf ] Wesley Peck , Erik Anderson , Jason Agron , Jim Stevens , Fabrice Baijot , David L. Andrews Hthreads: A Computational Model for Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Yongfeng Gu , Tom Van Court , Martin C. Herbordt Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Lysaght , Brandon Blodget , Jeff Mason , Jay Young , Brendan Bridgford Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Arfan Ghani , T. Martin McGinnity , Liam P. Maguire , Jim Harkin Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Danilin , Martijn T. Bennebroek , Sergei Sawitzki Astra: An Advanced Space-Time Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Minoru Watanabe , Fuminori Kobayashi A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Angel Quiros Olozabal , Ma de los Angeles Cifredo Chacon , Diego Gomez Vela FPGA-Based Boundary-Scan Bist. [Citation Graph (0, 0)][DBLP ] Conf ] Sándor P. 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Voros , Miroslav Cupák , Luc Rijnders , Marko Pettissalo System Level Architecture Exploration for Reconfigurable Systems On Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Dries Schellekens , Bart Preneel , Ingrid Verbauwhede FPGA Vendor Agnostic True Random Number Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Saldaña , Paul Chow TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Yoshimi , Yasunori Osana , Yow Iwaoka , Yuri Nishikawa , Toshinori Kojima , Akira Funahashi , Noriko Hiroi , Yuichiro Shibata , Naoki Iwanaga , Hiroaki Kitano , Hideharu Amano An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Love Singhal , Elaheh Bozorgzadeh Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten Bieser , Martin Bahlinger , Matthias Heinz , Christian Stops , Klaus D. Müller-Glaser A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Baptiste Note , Mark Shand , Jean Vuillemin Real-Time Video Pixel Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Osana , Masato Yoshimi , Akira Funahashi , Noriko Hiroi , Yuichiro Shibata , Naoki Iwanaga , Hiroaki Kitano , Hideharu Amano Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip. [Citation Graph (0, 0)][DBLP ] Conf ] María Brox , Santiago Sánchez-Solano Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Evangelia Kassapaki , Pavlos M. Mattheakis , Christos P. Sotiriou Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Hutton FPGA Architecture Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Lesley Shannon , Blair Fort , Samir Parikh , Arun Patel , Manuel Saldaña , Paul Chow A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Campregher , Peter Y. K. Cheung , George A. Constantinides , Milan Vasilko Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Imran Ahmed , Tughrul Arslan A Reconfigurable Viterbi Decoder for a Communication Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Pongstorn Maidee , Kia Bazargan Defect-Tolerant FPGA Architecture Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Saunders , Anthony D. Fagan A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Hristo Nikolov , Todor Stefanov , Ed F. Deprettere Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Danne , Roland Muhlenbernd , Marco Platzner Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions. [Citation Graph (0, 0)][DBLP ] Conf ] 