Conferences in DBLP

High Performance Embedded Architectures and Compilers (hipeac)
2007 (conf/hipeac/2007)

1. Thomas M. Conte
   Keynote: Insight, Not (Random) Numbers: An Embedded Perspective. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:3- [Conf]
   
2. Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy
   Compiler-Assisted Memory Encryption for Embedded Processors. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:7-22 [Conf]
   
3. Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
   Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:23-37 [Conf]
   
4. Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras
   Applying Decay to Reduce Dynamic Power in Set-Associative Caches. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:38-53 [Conf]
   
5. Jun Yan, Wei Zhang
   Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:57-70 [Conf]
   
6. Weihaw Chuang, Satish Narayanasamy, Brad Calder, Ranjit Jhala
   Bounds Checking with Taint-Based Analysis. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:71-86 [Conf]
   
7. Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
   Reducing Exit Stub Memory Consumption in Code Caches. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:87-101 [Conf]
   
8. Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
   Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:105-119 [Conf]
   
9. Hans Vandierendonck, André Seznec
   Fetch Gating Control Through Speculative Instruction Window Weighting. [Citation Graph (0, 0)][DBLP]
   HiPEAC, 2007, pp:120-135 [Conf]
   
10. Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
    Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:136-150 [Conf]
    
11. Simon Kluyskens, Lieven Eeckhout
    Branch History Matching: Branch Predictor Warmup for Sampled Simulation. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:153-167 [Conf]
    
12. Phillip Stanley-Marbell, Diana Marculescu
    Sunflower : Full-System, Embedded Microarchitecture Evaluation. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:168-182 [Conf]
    
13. Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
    Efficient Program Power Behavior Characterization. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:183-197 [Conf]
    
14. Paolo D'Alberto, Markus Püschel, Franz Franchetti
    Performance/Energy Optimization of DSP Transforms on the XScale Processor. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:201-214 [Conf]
    
15. Klaas L. Hofstra, Sabih H. Gerez
    Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:215-226 [Conf]
    
16. Lixia Liu, Xiao-Feng Li, Michael Chen, Roy Dz-Ching Ju
    A Throughput-Driven Task Creation and Mapping for Network Processors. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:227-241 [Conf]
    
17. Grigori Fursin, John Cavazos, Michael F. P. O'Boyle, Olivier Temam
    MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:245-260 [Conf]
    
18. Johnny Huynh, José Nelson Amaral, Paul Berube, Sid Ahmed Ali Touati
    Evaluation of Offset Assignment Heuristics. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:261-275 [Conf]
    
19. Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl
    Customizing the Datapath and ISA of Soft VLIW Processors. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:276-290 [Conf]
    
20. I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann
    Instruction Set Extension Generation with Considering Physical Constraints. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:291-305 [Conf]