Conferences in DBLP
Subhasish Mitra , Pia Sanda , Norbert Seifert Soft Errors: Technology Trends, System Effects, and Protection Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Derbey Soft-Errors Phenomenon Impacts on Design for Reliability Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjiv Taneja Accelerating Yield Ramp through Real-Time Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jaume Abella , Xavier Vera , Osman S. Unsal , Oguz Ergin , Antonio González Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. [Citation Graph (0, 0)][DBLP ] Conf ] Ming Zhang , T. M. Mak , James Tschanz , Kee Sup Kim , Norbert Seifert , Davia Lu Design for Resilience to Soft Errors and Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Somnath Paul , Rajat Subhra Chakraborty , Swarup Bhunia Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. [Citation Graph (0, 0)][DBLP ] Conf ] Cristian Grecu , Lorena Anghel , Partha Pratim Pande , André Ivanov , Resve Saleh Essential Fault-Tolerance Metrics for NoC Infrastructures. [Citation Graph (0, 0)][DBLP ] Conf ] Daniele Rossi , Paolo Angelini , Cecilia Metra Configurable Error Control Scheme for NoC Signal Integrity. [Citation Graph (0, 0)][DBLP ] Conf ] Atefe Dalirsani , Mohammad Hosseinabady , Zainalabedin Navabi An Analytical Model for Reliability Evaluation of NoC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Giorgio Di Natale , Marie-Lise Flottes , Bruno Rouzeyre An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] N. Buard , F. Miller , C. Ruby , R. Gaillard Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks? [Citation Graph (0, 0)][DBLP ] Conf ] Osama Al-Khaleel , Christos A. Papachristou , Francis G. Wolff , Kiamal Z. Pekmestzi An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos G. Bartzoudis , Klaus D. McDonald-Maier Online monitoring of FPGA-based co-processing engines embedded in dependable workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Pignol Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant Spacecraft Supercomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , Leonardo Piccoli , Juliano Benfica , Antonio A. de Alecrim Jr. , Marlon Moraes Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Marta Portela-García , Celia López-Ongil , Mario García-Valderas , Luis Entrena A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bernardi , Leticia Maria Veiras Bolzani , Matteo Sonza Reorda A Hybrid Approach to Fault Detection and Correction in SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick Monnet , Marc Renaudin , Régis Leveugle Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. [Citation Graph (0, 0)][DBLP ] Conf ] Antonis Papanikolaou , Hua Wang , Miguel Miranda , Francky Catthoor Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design. [Citation Graph (0, 0)][DBLP ] Conf ] T. M. Mak Infant Mortality--The Lesser Known Reliability Issue. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout. [Citation Graph (0, 0)][DBLP ] Conf ] Krisztián Flautner Blurring the Layers of Abstractions: Time to Take a Step Back? [Citation Graph (0, 0)][DBLP ] Conf ] Tino Heijmen Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] C. Rusu , A. Bougerol , L. Anghel , C. Weulersse , N. Buard , S. Benhammadi , N. Renaud , G. Hubert , F. Wrobel , T. Carriere , R. Gaillard Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells. [Citation Graph (0, 0)][DBLP ] Conf ] M. Bagatin , G. Cellere , S. Gerardin , A. Paccagnella , A. Visconti , S. Beltrami , M. Maccarrone Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions. [Citation Graph (0, 0)][DBLP ] Conf ] Alodeep Sanyal , Sandip Kundu On Derating Soft Error Probability Based on Strength Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Partha Pratim Pande , Amlan Ganguly , Brett Feero , Cristian Grecu Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge Semião , J. Freijedo , Juan J. Rodríguez-Andina , Fabian Vargas , Marcelino B. Santos , Isabel C. Teixeira , J. P. Teixeira On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad M. Nisar , Maryam Ashouei , Abhijit Chatterjee Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums. [Citation Graph (0, 0)][DBLP ] Conf ] X. Cano , Sebastià A. Bota , R. Graciani , D. Gascón , A. Herms , A. Comerma , Jaume Segura , L. Garrido Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Faurax , Assia Tria , Laurent Freund , Frédéric Bancel Robustness of circuits under delay-induced faults : test of AES with the PAFI tool. [Citation Graph (0, 0)][DBLP ] Conf ] Riccardo Mariani , Gabriele Boschi A systematic approach for Failure Modes and Effects Analysis of System-On-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Costas Argyrides , Dhiraj K. Pradhan Highly Reliable Power Aware Memory Design. [Citation Graph (0, 0)][DBLP ] Conf ] Alodeep Sanyal , Kunal P. Ganeshpure , Sandip Kundu Accelerating Soft Error Rate Testing Through Pattern Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Salvatore Pontarelli , Luca Sterpone , Gian-Carlo Cardarilli , Marco Re , Matteo Sonza Reorda , Adelio Salsano , Massimo Violante Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Ioannis Voyiatzis Embedding test patterns into Low-Power BIST sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrice Monteiro , Stanislaw J. Piestrak , Houssein Jaber , Abbas Dandache Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Ilia Polian , Damian Nowroth , Bernd Becker Identification of Critical Errors in Imaging Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Franz X. Ruckerbauer , Georg Georgakos Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Hosseinabady , Mohammad Hossein Neishaburi , Zainalabedin Navabi , Alfredo Benso , Stefano Di Carlo , Paolo Prinetto , Giorgio Di Natale Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Jimson Mathew , H. Rahaman , Dhiraj K. Pradhan Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. [Citation Graph (0, 0)][DBLP ] Conf ] Karthik Pattabiraman , Zbigniew Kalbarczyk , Ravishankar K. Iyer Automated Derivation of Application-aware Error Detectors using Static Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel G. Gericota , Luís F. Lemos , Gustavo R. Alves , José M. Ferreira On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] K. T. Gardiner , Alexandre Yakovlev , Alexandre V. Bystrov A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] John Liobe , Martin Margala Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanuel Simeu , Salvador Mir , R. Kherreddine , H. N. Nguyen Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Swaroop Ghosh , Patrick Ndai , Swarup Bhunia , Kaushik Roy Tolerance to Small Delay Defects by Adaptive Clock Stretching. [Citation Graph (0, 0)][DBLP ] Conf ] Asen Asenov Statistical Device Variability and its Impact on Yield and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Pandini Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis GRAAL: A Fault-Tolerant Architecture for Enabling Nanometric Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques Henri Collet , Piotr Zajac Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips. [Citation Graph (0, 0)][DBLP ] Conf ] Xavier Vera , Jaume Abella Surviving to Errors in Multi-Core Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Krisztián Flautner Architectural Trade-Offs for Fault Tolerant Multi-Core Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Leticia Maria Veiras Bolzani , E. Sanchez , Massimiliano Schillaci , Matteo Sonza Reorda , Giovanni Squillero An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. [Citation Graph (0, 0)][DBLP ] Conf ] A. Apostolakis , Mihalis Psarakis , Dimitris Gizopoulos , Antonis M. Paschalis A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] R. Frost Brandenburg , D. Rudolph , Christian Galke , René Kothe , Heinrich Theodor Vierhaus A Configurable Modular Test Processor and Scan Controller Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Tarnick Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters. [Citation Graph (0, 0)][DBLP ] Conf ] Snehal Udar , Dimitri Kagaris LFSR Reseeding with Irreducible Polynomials. [Citation Graph (0, 0)][DBLP ] Conf ] 