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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2007 (conf/isca/2007)

  1. David E. Shaw, Martin M. Deneroff, Ron O. Dror, Jeffrey Kuskin, Richard H. Larson, John K. Salmon, Cliff Young, Brannon Batson, Kevin J. Bowers, Jack C. Chao, Michael P. Eastwood, Joseph Gagliardo, J. P. Grossman, Richard C. Ho, Doug Ierardi, István Kolossváry, John L. Klepeis, Timothy Layman, Christine McLeavey, Mark A. Moraes, Rolf Mueller, Edward C. Priest, Yibing Shan, Jochen Spengler, Michael Theobald, Brian Towles, Stanley C. Wang
    Anton, a special-purpose machine for molecular dynamics simulation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:1-12 [Conf]
  2. Xiaobo Fan, Wolf-Dietrich Weber, Luiz André Barroso
    Power provisioning for a warehouse-sized computer. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:13-23 [Conf]
  3. Colin Blundell, Joe Devietti, E. Christopher Lewis, Milo M. K. Martin
    Making the fast case common and the uncommon case simple in unbounded transactional memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:24-34 [Conf]
  4. Weirong Zhu, Vugranam C. Sreedhar, Ziang Hu, Guang R. Gao
    Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:35-45 [Conf]
  5. Michael R. Marty, Mark D. Hill
    Virtual hierarchies to support server consolidation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:46-56 [Conf]
  6. Kyle J. Nesbit, James Laudon, James E. Smith
    Virtual private caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:57-68 [Conf]
  7. Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Bronson, Jared Casper, Christos Kozyrakis, Kunle Olukotun
    An effective hybrid transactional memory system with strong isolation guarantees. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:69-80 [Conf]
  8. Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood
    Performance pathologies in hardware transactional memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:81-91 [Conf]
  9. Hany E. Ramadan, Christopher J. Rossbach, Donald E. Porter, Owen S. Hofmann, Bhandari Aditya, Emmett Witchel
    MetaTM//TxLinux: transactional memory for an operating system. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:92-103 [Conf]
  10. Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott
    An integrated hardware-software approach to flexible transactional memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:104-115 [Conf]
  11. Pablo Abad, Valentin Puente, José-Ángel Gregorio, Pablo Prieto
    Rotary router: an efficient architecture for CMP interconnection networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:116-125 [Conf]
  12. John Kim, William J. Dally, Dennis Abts
    Flattened butterfly: a cost-efficient topology for high-radix networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:126-137 [Conf]
  13. Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
    A novel dimensionally-decomposed router for on-chip communication in 3D architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:138-149 [Conf]
  14. Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha
    Express virtual channels: towards the ideal interconnection fabric. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:150-161 [Conf]
  15. Sanjeev Kumar, Christopher J. Hughes, Anthony Nguyen
    Carbon: architectural support for fine-grained parallelism on chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:162-173 [Conf]
  16. Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles
    Hardware atomicity for reliable software speculation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:174-185 [Conf]
  17. Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez
    Core fusion: accommodating software diversity in chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:186-197 [Conf]
  18. Eric Chi, Stephen A. Lyon, Margaret Martonosi
    Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:198-209 [Conf]
  19. Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang
    A 64-bit stream processor architecture for scientific applications. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:210-219 [Conf]
  20. Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen
    Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:220-231 [Conf]
  21. Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman
    ParallAX: an architecture for real-time physics. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:232-243 [Conf]
  22. Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin
    Architectural implications of brick and mortar silicon manufacturing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:244-253 [Conf]
  23. Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson
    Aquacore: a programmable architecture for microfluidics. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:254-265 [Conf]
  24. Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos
    Mechanisms for store-wait-free multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:266-277 [Conf]
  25. Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas
    BulkSC: bulk enforcement of sequential consistency. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:278-289 [Conf]
  26. Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Ricardo Bianchini
    Limiting the power consumption of main memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:290-301 [Conf]
  27. Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau
    Power model validation through thermal measurements. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:302-311 [Conf]
  28. Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang
    Thermal modeling and management of DRAM memory systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:312-322 [Conf]
  29. Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas
    ReCycle: : pipeline adaptation to tolerate process variation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:323-334 [Conf]
  30. Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black
    Matrix scheduler reloaded. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:335-346 [Conf]
  31. Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler
    Late-binding: enabling unordered load-store queues. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:347-357 [Conf]
  32. Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis
    Comparing memory systems for chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:358-368 [Conf]
  33. Naveen Muralimanohar, Rajeev Balasubramonian
    Interconnect design considerations for large NUCA caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:369-380 [Conf]
  34. Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
    Adaptive insertion policies for high performance caching. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:381-391 [Conf]
  35. Paul A. Karger
    Performance and security lessons learned from virtualizing the alpha processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:392-401 [Conf]
  36. Tejas Karkhanis, James E. Smith
    Automated design of application specific superscalar processors: an analytical approach. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:402-411 [Conf]
  37. Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
    Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:412-423 [Conf]
  38. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn
    VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:424-435 [Conf]
  39. Andrew D. Hilton, Amir Roth
    Ginger: control independence using tag rewriting. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:436-447 [Conf]
  40. Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary
    Transparent control independence (TCI). [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:448-459 [Conf]
  41. Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
    Examining ACE analysis reliability estimates using fault-injection. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:460-469 [Conf]
  42. Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith
    Configurable isolation: building high availability systems with commodity multi-core processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:470-481 [Conf]
  43. Michael Dalton, Hari Kannan, Christos Kozyrakis
    Raksha: a flexible information flow architecture for software security. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:482-493 [Conf]
  44. Zhenghong Wang, Ruby B. Lee
    New cache designs for thwarting software cache-based side channel attacks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:494-505 [Conf]
  45. Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam
    Mechanisms for bounding vulnerabilities of processor structures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:506-515 [Conf]
  46. Kristen R. Walcott, Greg Humphreys, Sudhanva Gurumurthi
    Dynamic prediction of architectural vulnerability from microarchitectural state. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:516-527 [Conf]
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