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Conferences in DBLP

IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
2007 (conf/iscas/2007)

  1. Ramon Tortosa Navas, Antonio Aceituno, José Manuel de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández
    A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1-4 [Conf]
  2. Minho Kwon, Gunhee Han
    An I/Q Channel Time-Interleaved Band-Pass Sigma-Delta Modulator for a Low-IF Receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:5-8 [Conf]
  3. Jens Anders, Wolfgang Mathis
    On the modeling and the stability of continuous-time Sigma-Delta-Modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:9-12 [Conf]
  4. Christopher S. Taillefer, Gordon W. Roberts
    Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:13-16 [Conf]
  5. Xavier Redondo, Jofre Pallares, Francisco Serra-Graells
    A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:17-20 [Conf]
  6. Ediz Çetin, Izzet Kale, Richard C. S. Morling
    Living and Dealing with RF Impairments in Communication Transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:21-24 [Conf]
  7. Lauri Anttila, Mikko Valkama, Markku Renfors
    3.9G Radio Reception with SC-FDMA Waveforms Under I/Q Imbalance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:25-28 [Conf]
  8. Piotr Rykaczewski, Friedrich Jondral
    Blind I/Q Imbalance Compensation in Multipath Environments. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:29-32 [Conf]
  9. Marcus Windisch, Gerhard Fettweis
    On the Impact of I/Q Imbalance in Multi-Carrier Systems for Different Channel Scenarios. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:33-36 [Conf]
  10. Qiyue Zou, Alireza Tarighat, Ali H. Sayed
    On the Joint Compensation of IQ Imbalances and Phase Noise in MIMO-OFDM Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:37-40 [Conf]
  11. Mei Guo, Yan Lu, Feng Wu, Shipeng Li, Wen Gao
    Distributed Video Coding with Spatial Correlation Exploited Only at the Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:41-44 [Conf]
  12. Zhihai He
    Peak Transform for Efficient Image Representation and Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:45-48 [Conf]
  13. Long Xu, Wen Gao, Xiangyang Ji, Debin Zhao
    Rate Control for Hierarchical B-picture Coding with Scaling-factors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:49-52 [Conf]
  14. Yong Fang, Lu Yu
    Block-Interleaved Error-Resilient Entropy Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:53-56 [Conf]
  15. Shilin Xu, Li Yu, Guangxi Zhu
    A Perceptual Coding Method based on the Luma Sensitivity Model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:57-60 [Conf]
  16. Hanoch Lev-Ari, Alex M. Stankovic
    Fundamental Performance Limits in Lossy Polyphase Systems: Apparent Power and Optimal Compensation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:61-64 [Conf]
  17. Ali Pinar, Adam Reichert, Bernard C. Lesieutre
    Computing Criticality of Lines in Power Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:65-68 [Conf]
  18. Bei Gou, Hui Zheng, Weibiao Wu, Xingbin Yu
    Probability Distribution of Blackouts in Complex Power Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:69-72 [Conf]
  19. Aaron St. Leger, Juan C. Jimenez, Agung Fu, Sanal Djimbinov, Sa Em Soeurn, Sun Sit Lwin, Chika O. Nwankpa
    Analog Emulation of a Reconfigurable Tap Changing Transformer. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:73-76 [Conf]
  20. Hiroyuki Mori, Hidenobu Tani
    Application of Two-Layered Tabu Search to Optimal Allocation of D-FACTS for Uncertain Wind Power Generation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:77-80 [Conf]
  21. Clyde Clarke, Carl White, Ralph Etienne-Cummings
    Design and Optimization of a Capacitive Micromachined Ultrasonic Transducer Micro-Array for Near Field Sensing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:81-84 [Conf]
  22. Ebrahim Ghafar-Zadeh, Mohamad Sawan
    A CMOS-Based Capacitive Sensor for Laboratory-On-Chips: Design and Experimental Results. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:85-88 [Conf]
  23. Nizar Lajnef, Shantanu Chakrabartty, Niell Elvin, Alex Elvin
    Piezo-powered floating gate injector for self-powered fatigue monitoring in biomechanical implants. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:89-92 [Conf]
  24. N. Safavian, G. Reza Chaji, S. J. Ashtiani, Arokia Nathan, John A. Rowlands
    A novel current scaling active pixel sensor with correlated double sampling readout circuit for real time medical x-ray imaging. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:93-96 [Conf]
  25. Andrea Anzalone, Federico Bizzarri, Paolo Camera, Luca Petrillo, Marco Storace
    DSP implementation of a low-complexity algorithm for real-time automated vessel detection in images of the fundus of the human retina. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:97-100 [Conf]
  26. Raghuram Ranganathan, Wasfy B. Mikhael
    A Novel Interference Supression Technique employing Complex Adaptive ICA for Time-Varying Channels in Diversity Wireless QAM Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:101-104 [Conf]
  27. Da-Zheng Feng, Wei Xing Zheng
    Adaptive IIR Filtering via a Recursive Total Instrumental Variable Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:105-108 [Conf]
  28. Munkyo Seo, Mark J. W. Rodwell
    Generalized Blind Mismatch Correction for a Two-Channel Time-Interleaved ADC: Analytic Approach. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:109-112 [Conf]
  29. Jeffrey A. Foutz, Andreas S. Spanias
    An Adaptive Low Rank Algorithm for Semispherical Antenna Arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:113-116 [Conf]
  30. Paulo Alexandre Crisóstomo Lopes, José Beltran Gerald
    New Normalized LMS Algorithms Based on the Kalman Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:117-120 [Conf]
  31. Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
    Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:121-124 [Conf]
  32. Héctor Pettenghi, Maria J. Avedillo, José M. Quintana
    Non Return Mobile Logic Family. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:125-128 [Conf]
  33. Takao Waho, Akinori Yamada, Hiroki Okuyama, Victor Khorenko, Thai Do, Werner Prost
    A Four-Resonant-Tunneling-Diode (4RTD) NAND/NOR Logic Gate. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:129-132 [Conf]
  34. Jacques-Olivier Klein, Eric Belhaire, Claude Chappert, Florent Ouchet, Russell Cowburn, Dan Read, Dorothee Petit
    Synthesis of Finite State Machines with Magnetic Domain Wall Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:133-136 [Conf]
  35. Jennifer Blain Christen, Andreas G. Andreou
    A Self-Biased Operational Transconductance Amplifier in 0.18 micron 3D SOI-CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:137-140 [Conf]
  36. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:141-144 [Conf]
  37. Jing Li, Hiroshi Miyashita
    Efficient Thermal Via Planning for Placement of 3D Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:145-148 [Conf]
  38. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
    Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:149-152 [Conf]
  39. Xueqing Wang, William R. Eisenstadt, Robert M. Fox
    Embedded Jitter Measurement of High-speed I/O Signals. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:153-156 [Conf]
  40. Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
    GALS Based Shared Test Architecture for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:157-160 [Conf]
  41. Yang Qu, Juha-Pekka Soininen, Jari Nurmi
    A Genetic Algorithm for Scheduling Tasks onto Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:161-164 [Conf]
  42. Fredrik Kristensen, W. James MacLean
    Real-Time Extraction of Maximally Stable Extremal Regions on an FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:165-168 [Conf]
  43. Christopher M. Twigg, Jordan D. Gray, Paul E. Hasler
    Programmable Floating Gate FPAA Switches Are Not Dead Weight. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:169-172 [Conf]
  44. Christopher M. Twigg, Paul E. Hasler
    Programmable Conductance Switches for FPAAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:173-176 [Conf]
  45. Paul E. Hasler, Christopher M. Twigg
    An OTA-based Large-Scale Field Programmable Analog Array (FPAA) for faster On-Chip Communication and Computation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:177-180 [Conf]
  46. Boo-Young Choi, Jung-Won Han, Sung Min Park, Kang Yeob Park, Won-S. Oh, J.-C. Choi
    A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:181-184 [Conf]
  47. David Rennie, Manoj Sachdev
    A Novel Tri-State Binary Phase Detector. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:185-188 [Conf]
  48. Mike Bichan, Anthony Chan Carusone
    Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:189-192 [Conf]
  49. Hyoungsoo Kim, Franklin Bien, Youngsik Hur, Soumya Chandramouli, J. Cha, Edward Gebara, Joy Laskar
    A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:193-196 [Conf]
  50. Franklin Bien, Soumya Chandramouli, Hyoungsoo Kim, Edward Gebara, Joy Laskar
    Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:197-200 [Conf]
  51. Tetsuro Endo, Jun Yokota
    Generation of White Noise by Using Chaos in Practical Phase-Locked Loop Integrated Circuit Module. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:201-204 [Conf]
  52. Ned J. Corron, Scott T. Hayes, Shawn D. Pethel, Jonathan N. Blakely
    Reverse-Time Chaos from a Randomly Driven Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:205-208 [Conf]
  53. Yoko Uwate, Yoshifumi Nishio
    Switching Phase States of Chaotic Circuits Coupled by Time-Varying Resistor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:209-212 [Conf]
  54. Sergio Callegari, Gianluca Setti
    ADCs, Chaos and TRNGs: a Generalized View Exploiting Markov Chain Lumpability Properties. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:213-216 [Conf]
  55. Weihua Deng, Jinhu Lu
    Design of Multi-Directional Multi-Scroll Chaotic Attractors Based on Fractional Differential Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:217-220 [Conf]
  56. Chutham Sawigun, Jirayuth Mahattanakul
    A Compact High Current Efficiency Low-Voltage MOS Transconductor with Nearly Constant Input Voltage Range. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:221-224 [Conf]
  57. Jingjing Hu, Johan H. Huijsing, Kofi A. A. Makinwa
    A Three-Stage Amplifier with Quenched Multipath Frequency Compensation for All Capacitive Loads. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:225-228 [Conf]
  58. T. Hui Teo, Wooi Gan Yeoh
    Low-Power Digitally Controlled CMOS Source Follower Variable Attenuator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:229-232 [Conf]
  59. Hirokazu Yoshizawa, Gabor C. Temes
    Predictive Switched-Capacitor Track-and-Hold Amplifier with Improved Linearity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:233-236 [Conf]
  60. Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
    150 µA CMOS Transconductor with 82 dB SFDR. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:237-240 [Conf]
  61. Matthias Keller, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli
    A Method for the Discrete-Time Simulation of Continuous-Time Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:241-244 [Conf]
  62. Chi-Tung Ko, Kong-Pang Pun
    A DEM Scheme for I/Q Mismatch Compensation in Multi-Bit CT Delta Sigma Modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:245-248 [Conf]
  63. Kyehyung Lee, Gabor C. Temes, Franco Maloberti
    Noise-Coupled Multi-Cell Delta-Sigma ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:249-252 [Conf]
  64. Ghyslain Gagnon, Leonard MacEachern
    Continuous Compensation of Binary-Weighted DAC Nonlinearities in Bandpass Delta-Sigma Modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:253-256 [Conf]
  65. Nima Maghari, Sunwoo Kwon, Gabor C. Temes, Un-Ku Moon
    Mixed-Order Sturdy MASH Delta-Sigma Modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:257-260 [Conf]
  66. Timo Roman, Visa Koivunen
    Carrier frequency synchronization for mobile television receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:261-264 [Conf]
  67. Xinping Huang, Mario Caron
    Efficient Transmitter Self-Calibration and Amplifier Linearization Techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:265-268 [Conf]
  68. Antonio Cantoni, John Tuthill
    Digital Compensation of Frequency Dependent Imperfections in Direct Conversion I-Q Modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:269-272 [Conf]
  69. Eric A. M. Klumperink, Rameswor Shrestha, Eisse Mensink, Gerard Wienk, Zhiyu Ru, Bram Nauta
    Multipath Polyphase Circuits and their Application to RF Transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:273-276 [Conf]
  70. Kutluyil Dogancay
    Adaptive Pre-Distortion of Nonlinear Systems Using Out-of-Band Energy Minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:277-280 [Conf]
  71. Jie Dong, King Ngi Ngan, Chi-Keung Fong, Wai-Kuen Cham
    A Universal Approach to Developing Fast Algorithm for Simplified Order-16 ICT. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:281-284 [Conf]
  72. Jiancong Luo, Yu Sun, Ishfaq Ahmad
    A PD Feed-back Rate Control Algorithm for Multiple Video Object Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:285-288 [Conf]
  73. Jianpeng Dong, Nam Ling
    On Model Parameter Estimation for H.264/AVC Rate Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:289-292 [Conf]
  74. Jun Zhang, Xiaoquan Yi, Nam Ling, Weijia Shang
    Chroma Coding Efficiency Improvement with Context Adaptive Lagrange Multiplier (CALM). [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:293-296 [Conf]
  75. Jingyu Yang, Wenli Xu, Qionghai Dai, Yao Wang
    Image Compression using 2D Dual-tree Discrete Wavelet Transform (DDWT). [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:297-300 [Conf]
  76. Philippe Artillan, Bruno Estibals, Alain Salles, Jean Abboud, Pierre Aloisi, Corinne Alonso
    A PEEC approach for circular spiral inductive components modeling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:301-304 [Conf]
  77. Feng Luo, Dongsheng Ma
    An Integrated Switching Power Converter with a Hybrid Pulse-Train/PWM Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:305-308 [Conf]
  78. Vincent Binet, Yvon Savaria, Michel Meunier, Yves Gagnon
    Modeling the Substrate Noise Injected by a DC-DC Converter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:309-312 [Conf]
  79. Bharath Balaji Kannan, Khai D. T. Ngo
    Digital Inverse Timing Generator with Wide Dynamic Range. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:313-316 [Conf]
  80. Alessandro Cabrini, L. Gobbi, Guido Torelli
    Design of Maximum-Efficiency Integrated Voltage Doubler. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:317-320 [Conf]
  81. Ming Yin, Maysam Ghovanloo
    A Low-Noise Preamplifier with Adjustable Gain and Bandwidth for Biopotential Recording Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:321-324 [Conf]
  82. Jim Simpson, Maysam Ghovanloo
    An Experimental Study of Voltage, Current, and Charge Controlled Stimulation Front-End Circuitry. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:325-328 [Conf]
  83. AbdEl-Monem M. El-Sharkawy, Paul-Peter Sotiriadis, Paul A. Bottomley, Ergin Atalar
    A New RF Radiometer for Absolute Noninvasive Temperature Sensing in Biomedical Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:329-332 [Conf]
  84. Chae-Ryung Kim, Yu-Ri Kang, Young-Jae Min, Soo-Won Kim
    A 2.5-V 4-µW Low-Power Delta-Sigma Modulator for Implantable Cardiac Pacemaker with Periodic Bias Current Reduction Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:333-336 [Conf]
  85. Chiu-Hsien Chan, Jack Wills, Jeff LaCoss, John J. Granacki, John Choma Jr.
    A Novel Variable-Gain Micro-Power Band-Pass Auto-Zeroing CMOS Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:337-340 [Conf]
  86. Huimin Chen, Dimitrios Charalampidis
    Fast Basis Selection and Instantaneous Frequency Tracking for Audio Signal Analysis and Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:341-344 [Conf]
  87. Talieh Seyed Tabatabaei, Sridhar Krishnan, Aziz Guergachi
    Emotion Recognition Using Novel Speech Signal Features. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:345-348 [Conf]
  88. S. A. Fattah, Wei-Ping Zhu, M. Omair Ahmad
    An Identification Technique for Noisy ARMA Systems in Correlation Domain. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:349-352 [Conf]
  89. Zohra Yermeche, Benny Sallberg, Nedelko Grbic, Ingvar Claesson
    Real-Time DSP Implementation of a Subband Beamforming Algorithm for Dual Microphone Speech Enhancement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:353-356 [Conf]
  90. Han Jae Hee, Myung Hoon Sunwoo, Jong Ha Moon
    Novel Non-linear Inverse Quantization Algorithm and its Architecture for Digital Audio Codecs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:357-360 [Conf]
  91. Teijo Lehtonen, Pasi Liljeberg, Juha Plosila
    Fault Tolerance Analysis of NoC Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:361-364 [Conf]
  92. Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan
    Multiple Upsets Tolerance in SRAM Memory. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:365-368 [Conf]
  93. Themistoklis Prodromakis, Christos Papavassiliou, George Konstantinidis
    A Miniaturized Delay Line based on Slow-Wave Substrates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:369-372 [Conf]
  94. Wai-Chi Fang, Sharon Kedar
    Gigascale System Design of Sensor Networks for Active Volcanoes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:373-376 [Conf]
  95. Pier Paolo Civalleri, Marco Gilli, Michele Bonnin
    Open Two-State Quantum Systems Solved by Harmonic Balance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:377-380 [Conf]
  96. Sumit D. Mediratta, Jeffrey T. Draper
    Characterization of a Fault-tolerant NoC Router. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:381-384 [Conf]
  97. Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai
    Fast Fair Crossbar Scheduler for On-chip Router. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:385-388 [Conf]
  98. César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes
    Evaluation of Algorithms for Low Energy Mapping onto NoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:389-392 [Conf]
  99. Paul-Peter Sotiriadis
    An Information Theory Approach to Power - Optimal Trafic Routing in Networks on Chips. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:393-396 [Conf]
  100. Ik-Jae Chun, Tae Moon Roh, Bo-Gwan Kim
    Binary-Truncated CDMA-Based On-Chip Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:397-400 [Conf]
  101. Minoru Watanabe, Fuminori Kobayashi
    Holographic memory reconfigurable VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:401-404 [Conf]
  102. Christophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer
    Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:405-408 [Conf]
  103. Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu
    Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:409-412 [Conf]
  104. Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
    Visualization of SystemC Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:413-416 [Conf]
  105. Sayed Hafizur Rahman, Asif Iqbal Ahmed, Otmane Aït Mohamed
    Analysis and Performance Evaluation of a Digital Carrier Synchronizer for Modem Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:417-420 [Conf]
  106. Andrea Gerosa, M. Soldan, Alessandro Bevilacqua, Andrea Neviani
    A 0.18-µm CMOS Squarer Circuit for a Non-Coherent UWB Receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:421-424 [Conf]
  107. Yu-Tso Lin, Tao Wang, Shey-Shi Lu
    A Fully Integrated Concurrent Dual-Band Low Noise Amplifier with Suspended Inductors in SiGe 0.35µm BiCMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:425-428 [Conf]
  108. Rangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, Edgar Sánchez-Sinencio
    A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:429-432 [Conf]
  109. Saeed Sarhangian, Seyed Mojtaba Atarodi
    A Low-Power CMOS Low-IF Receiver Front-End for 2450-MHz Band IEEE 802.15.4 ZigBee Standard. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:433-436 [Conf]
  110. Zhujin Zhou, Ning Li, Wei Li, Junyan Ren
    A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:437-440 [Conf]
  111. Heinz Koeppl
    The Composition Rule for Multivariate Volterra Operators and its Application to Circuit Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:441-444 [Conf]
  112. Kofi M. Odame, Christopher M. Twigg, Arindam Basu, Paul E. Hasler
    Studying Nonlinear Dynamical Systems on a Reconfigurable Analog Platform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:445-448 [Conf]
  113. Guoji Zhu, Ajoy Opal
    Per-Element Decompostion in Distortion Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:449-452 [Conf]
  114. Wai M. Tam, Francis C. M. Lau, Chi K. Michael Tse
    Modeling the Telephone Call Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:453-456 [Conf]
  115. Andrew Buschmeier, Douglas Frey
    Novel Analysis of Phase Noise in Oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:457-460 [Conf]
  116. Belén Calvo, Santiago Celma, Maria Teresa Sanz, Juan P. Alegre
    Low-Voltage Linearly Tunable CMOS Transconductor with Common-Mode Feedforward. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:461-464 [Conf]
  117. Burak Kelleci, Edgar Sánchez-Sinencio, Aydin I. Karsilayan
    THD+Noise Estimation in Class-D Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:465-468 [Conf]
  118. Gianluca Giustolisi
    Two-Stage OTA Design Based on Settling-Time Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:469-472 [Conf]
  119. Ramón González Carvajal, Juan Antonio Gómez Galán, Antonio B. Torralba, C. Lujan-Martinez, Jaime Ramírez-Angulo, Antonio J. López-Martín
    A Very Linear OTA with V-I Conversion based on Quasi-Floating MOS Resistor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:473-476 [Conf]
  120. Tongyu Song, Shouli Yan
    A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:477-480 [Conf]
  121. Zhenyong Zhang, Gabor C. Temes
    A Segmented Data-Weighted-Averaging Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:481-484 [Conf]
  122. Yi Tang, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot
    A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:485-488 [Conf]
  123. Long-Xi Chang, Day-Uei Li, Chi-Chen Chung, Tim-Kuei Shia
    A 0.9mA 95dB Sigma Delta Modulator for Digital RF Hearing Aid in 0.35µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:489-492 [Conf]
  124. Sudhakar Pamarti
    A Theoretical Analysis of Split Delta-Sigma ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:493-496 [Conf]
  125. Philip M. Chopp, Anas A. Hamoui
    Discrete-Time Modeling of Clock Jitter in Continuous-Time Delta Sigma Modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:497-500 [Conf]
  126. Florin Constantinescu, Angelo Brambilla, Giancarlo Storti Gajani, Miruna Nitescu
    Algorithmic aspects in RF Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:501-504 [Conf]
  127. Thomas J. Brazil
    Nonlinear, Transient Simulation of Distributed RF Circuits using Discrete-Time Convolution. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:505-508 [Conf]
  128. Hans Georg Brachtendorf, Angelika Bunse-Gerstner, Barbara Lang, Rainer Laur
    An inverse method of characteristics for analyzing circuits with widely separated time-scales. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:509-512 [Conf]
  129. Alper Demir
    Noise Analysis Problems and Techniques for RF Electronic Circuits and Optical Fiber Communication Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:513-516 [Conf]
  130. Mihai Iordache, Lucia Dumitriu
    Multi-Time Method Based on State Equations for RF Circuit Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:517-520 [Conf]
  131. Jingjing Fu, Bing Zeng
    A Comparative Study of Compensation Techniques in Directional DCT's. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:521-524 [Conf]
  132. Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
    Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:525-528 [Conf]
  133. Qiang Hao, Xiangyang Ji, Qingming Huang, Debin Zhao, Wen Gao, Xilin Chen
    Macroblock-level Reduced Resolution Video Coding Allowing Adaptive DCT Coefficients Selection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:529-532 [Conf]
  134. Honggang Qi, Wen Gao
    High-Accuracy and Low-Complexity Fixed-Point Inverse Discrete Cosine Transform Based on AAN's Fast Algortihm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:533-536 [Conf]
  135. Li Zhang, Wen Gao, Qiang Wang, Debin Zhao
    Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:537-540 [Conf]
  136. Tadashi Suetsugu, Marian K. Kazimierczuk
    Output Characteristics of Class E Amplifier With Nonlinear Shunt Capacitance Versus Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:541-544 [Conf]
  137. Hsin-Hsin Ho, Ke-Horng Chen, Wen Tsao Chen
    Dynamic Droop Scaling for Improving Current Sharing Performance in a System with Multiple Supplies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:545-548 [Conf]
  138. Neeraj Keskar, Gabriel A. Rincón-Mora
    Designing an Accurate and Robust LC-Compliant Asynchronous Sigma Delta Boost DC-DC Converter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:549-552 [Conf]
  139. Hirotaka Koizumi, Kosuke Kurokawa
    Class DE Inverter with Asymmetric Shunt Capacitors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:553-556 [Conf]
  140. Hong Chen, Chen Jia, Chun Zhang, Zhihua Wang, Chunsheng Liu
    Power Harvesting With PZT Ceramics. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:557-560 [Conf]
  141. Robert Rieger, Yen-Yow Pan, John Taylor
    Design Strategies for Multi-Channel Low-Noise Recording Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:561-564 [Conf]
  142. Craig Hyatt
    Wireless Stimulus-Reflex Detection for Neonatal Monitoring. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:565-568 [Conf]
  143. Xiang Fang, Jack Wills, John Granacki, Jeff LaCoss, Artak Arakelian, James D. Weiland
    Novel Charge-Metering Stimulus Amplifier for Biomimetic Implantable Prosthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:569-572 [Conf]
  144. Maurits Ortmanns
    Charge Balancing in Functional Electrical Stimulators: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:573-576 [Conf]
  145. Cheng Chih Liu
    A 70dB Gain Low-Power Band-Pass Amplifier for Bio-Signals Sensing Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:577-580 [Conf]
  146. Chao Wu, Wei-Ping Zhu, M. N. S. Swamy
    A Class of Cosine-Modulated Filter Banks with Multiple Prototype Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:581-584 [Conf]
  147. H. H. Kha, H. D. Tuan, T. Q. Nguyen
    Design of Cosine-Modulated Pseudo-QMF Banks Using Semidefinite Programming Relaxation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:585-588 [Conf]
  148. Thushara K. Gunaratne, Leonard T. Bruton
    Beamforming of Temporally-Broadband-Bandpass Plane Waves using Real Polyphase 2-D FIR Trapezoidal Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:589-592 [Conf]
  149. Ligang Wu, James Lam, Wojciech Paszke, Krzysztof Galkowski, Eric Rogers, Anton Kummert
    Filtering of Discrete Linear Repetitive Processes with H and l2-l Performance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:593-596 [Conf]
  150. Zhiping Lin, Li Xu, Yoshihisa Anazawa
    Revisiting the Absolutely Minimal Realization for Two-dimensional Digital Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:597-600 [Conf]
  151. Bertram Emil Shi, Csaba Rekeczky
    Sensor Integration in Autonomous Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:601-604 [Conf]
  152. Timothy K. Horiuchi, Matthew Cheely
    A Systems View of a Neuromorphic VLSI Echolocation System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:605-608 [Conf]
  153. Paolo Arena, Luigi Fortuna, Mattia Frasca, Luca Patané, C. Sala
    Integrating high-level sensor features via STDP for bio-inspired navigation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:609-612 [Conf]
  154. Francesco Tenore, R. Jacob Vogelstein, Ralph Etienne-Cummings
    Sensor-based Dynamic Control of the Central Pattern Generator for Locomotion. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:613-616 [Conf]
  155. Gergely Balazs Soos, Csaba Rekeczky
    Elastic Grid Based Analysis of Motion Field for Object-Motion Detection in Airborne Video Flows. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:617-620 [Conf]
  156. Abinash Roy, Noha Mahmoud, Masud H. Chowdhury
    Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:621-624 [Conf]
  157. Himanshu Thapliyal, A. Prasad Vinod
    Design of Reversible Sequential Elements With Feasibility of Transistor Implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:625-628 [Conf]
  158. Syed Rafay Hasan, Yvon Savaria
    Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:629-632 [Conf]
  159. Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria
    A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:633-636 [Conf]
  160. O. Sarbishei, M. Maymandi-Nejad
    Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:637-640 [Conf]
  161. Jonathan Rosenfeld, Eby G. Friedman
    Quasi-Resonant Interconnects: A Low Power Design Methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:641-644 [Conf]
  162. Sherif A. Tawfik, Volkan Kursun
    Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:645-648 [Conf]
  163. Ethiopia Nigussie, Juha Plosila, Jouni Isoaho
    Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:649-652 [Conf]
  164. Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud
    Wavelet-Based Interpolation Point Selection for Multi-Shifted Arnoldi. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:653-656 [Conf]
  165. Xiongfei Meng, Karim Arabi, Resve Saleh
    A Novel Active Decoupling Capacitor Design in 90nm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:657-660 [Conf]
  166. P. P. Vaidyanathan
    On the degree of MIMO systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:661-664 [Conf]
  167. Se-Hyeon Kang, In-Cheol Park
    High Speed Sphere Decoding Based on Vertically Incremental Computation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:665-668 [Conf]
  168. Omid Oliaei
    Beamforming MIMO Receiver with Reduced Hardware Complexity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:669-672 [Conf]
  169. Andreas Burg, Dominik Seethaler, Gerald Matz
    VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:673-676 [Conf]
  170. Wen-Chih Kan, Gerald E. Sobelman
    MIMO Transceiver Design Based on a Modified Geometric Mean Decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:677-680 [Conf]
  171. Hsuan-Yu Marcus Pan, Lawrence E. Larson
    Improved Dynamic Model of Fast-Settling Linear-in-dB Automatic Gain Control Circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:681-684 [Conf]
  172. Martin Di Federico, Pedro Julian, Tomaso Poggi, Marco Storace
    A Simplicial PWL Integrated Circuit Realization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:685-688 [Conf]
  173. Jaime Ramírez-Angulo, Raghavender Chintham, Antonio J. López-Martín, Ramón González Carvajal
    Class AB Pseudo-Differential CMOS Squarer Circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:689-692 [Conf]
  174. Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
    Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:693-696 [Conf]
  175. Simin Yu, Wallace Kit-Sang Tang, Guanrong Chen
    From n-scroll to n-scroll attractors: A general structure based on Chua's circuit framework. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:697-700 [Conf]
  176. Tong Ge, Joseph Sylvester Chang, Wei Shu
    Power Supply Noise in Bang-Bang Control Class D Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:701-704 [Conf]
  177. S. Alireza Zabihian, Reza Lotfi
    Ultra-Low-Voltage, Low-Power, High-Speed Operational Amplifiers Using Body-Driven Gain-Boosting Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:705-708 [Conf]
  178. Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria
    Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:709-712 [Conf]
  179. Hsuan-Yu Marcus Pan, Lawrence E. Larson
    Highly Linear Bipolar Transconductor For Broadband High-Frequency Applications with Improved Input Voltage Swing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:713-716 [Conf]
  180. Behnam Sedighi, Mehrdad Sharif Bakhtiar
    A New High-Speed Class-AB Current-Mode Circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:717-720 [Conf]
  181. Matthias Keller, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli
    On the Implicit Anti-Aliasing Feature of Continuous-Time Multistage Noise-Shaping Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:721-724 [Conf]
  182. Alonso Morgado, Rocio del Río, José Manuel de la Rosa
    Design of a 130-nm CMOS Reconfigurable Cascade Sigma Delta Modulator for GSM/UMTS/Bluetooth. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:725-728 [Conf]
  183. Jaswinder Lota, Mohammed Al-Janabi, Izzet Kale
    Tonality Index of Sigma-Delta Modulators : A Psychoacoustics Model Based Approach. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:729-732 [Conf]
  184. Sunwoo Kwon, Un-Ku Moon
    A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:733-736 [Conf]
  185. Ling Yuan, Weining Ni, Yin Shi, Foster F. Dai
    A 10-bit 2GHz Current-Steering CMOS D/A Converter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:737-740 [Conf]
  186. Behzad Razavi
    Design Considerations for Future RF Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:741-744 [Conf]
  187. M. Sanduleanu, M. Vidojkovic, Vojkan Vidojkovic, Arthur H. M. van Roermund, Aleksandar Tasic
    Receiver Front-End Circuits for Future Generations of Wireless Communications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:745-748 [Conf]
  188. Vaibhav Maheshwari, Wouter A. Serdijn, John R. Long
    Companding Baseband Switched Capacitor Filters and ADCs for WLAN Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:749-752 [Conf]
  189. Lawrence Larson, Peter Asbeck, Donald Kimball
    Multifunctional RF Transmitters for Next Generation Wireless Transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:753-756 [Conf]
  190. John F. M. Gerrits, John R. Farserotu, John R. Long
    Low-Complexity Ultra Wideband Communications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:757-760 [Conf]
  191. Jer-Min Hsiao, Chun-Jen Tsai
    Analysis of an SOC Architecture for MPEG Reconfigurable Video Coding Framework. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:761-764 [Conf]
  192. Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
    Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:765-768 [Conf]
  193. Ulf Ochsenfahrt, Ralf Salomon
    CREMA: A Parallel Hardware Raytracing Machine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:769-772 [Conf]
  194. Li-Chuan Chang, Yen-Sung Chen, Rung-Wen Liou, Chih-Hung Kuo, Chia-Hung Yeh, Bin-Da Liu
    A Real Time and Low Cost Hardware Architecture for Video Abstraction System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:773-776 [Conf]
  195. Peilin Liu, Lingzhi Liu, Ning Deng, Xuan Fu, Jiayan Liu, Qianru Liu, Guocheng Zhang, Bin He
    VLSI Implementation for Portable Application Oriented MPEG-4 Audio Codec. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:777-780 [Conf]
  196. Wisam Al-Hoor, Jaber A. Abu-Qahouq, Lilly Huang, Issa Batarseh
    Adaptive Variable Switching Frequency Digital Controller Algorithm to Optimize Efficiency. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:781-784 [Conf]
  197. Huan-Jen Yang, Ke-Horng Chen, Yung-Pin Lee
    Feed-Forward Pulse Width Modulation for High Line Regulation Buck or Boost Converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:785-788 [Conf]
  198. Yuki Ishikawa, Toshimichi Saito
    Bifurcation of multiple-input parallel dc-dc converters with dynamic winner-take-all switching. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:789-792 [Conf]
  199. Ali Davoudi, Juri Jatskevich, Patrick L. Chapman
    Computer-Aided Average-Value Modeling of Fourth-Order PWM DC-DC Converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:793-796 [Conf]
  200. Dong Dai, Shengnan Li, Xikui Ma, Chi K. Michael Tse
    Hopf-Type Intermediate-Scale Bifurcation in Single-Stage Power-Factor-Correction Power Supplies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:797-800 [Conf]
  201. Suresh Atluri, Maysam Ghovanloo
    Incorporating Back Telemetry in a Full-Wave CMOS Rectifier for RFID and Biomedical Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:801-804 [Conf]
  202. Donghwi Kim, Ridha Kamoua, Milutin Stanacevic
    Low-Power Low-Noise Neural Amplifier in 0.18µm FD-SOI Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:805-808 [Conf]
  203. Marc Simon Wegmueller, Martin Hediger, Thomas Kaufmann, Felix Bürgin, Wolfgang Fichtner
    Wireless Implant Communications for Biomedical Monitoring Sensor Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:809-812 [Conf]
  204. T. Tam, Graham A. Jullien, Orly Yadid-Pecht
    A CMOS Contact Imager for Cell Detection in Bio-Sensing Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:813-816 [Conf]
  205. Edward K. F. Lee, Anthony Lam
    A Matching Technique for Biphasic Stimulation Pulse. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:817-820 [Conf]
  206. Hoda Mohammadzade, Leonard T. Bruton
    A Simultaneous Div-Curl 2D Clifford Fourier Transform Filter for Enhancing Vortices, Sinks and Sources in Sampled 2D Vector Field Images. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:821-824 [Conf]
  207. Magdy T. Hanna
    Direct Batch Evaluation of Desirable Eigenvectors of the DFT Matrix by Constrained Optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:825-828 [Conf]
  208. Da-Zheng Feng, Wei Xing Zheng
    An Efficient Identification Algorithm for FIR Filtering with Noisy Data. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:829-832 [Conf]
  209. Z. G. Zhang, S. C. Chan, V. W. Zhang, B. McPherson
    A New Minimum Variance Spectral Estimation Method for Analyzing Click-Evoked Otoacoustic Emissions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:833-836 [Conf]
  210. Hee Ju Park, Kyung Bum Kim, Jeong Hun Kim, Suki Kim
    A novel motion detection pointing device Using a binary CMOS image sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:837-840 [Conf]
  211. Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, A. Acosta-Jimenez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno, Antón Civit-Balcells, Bernabé Linares-Barranco
    Spike Events Processing for Vision Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:841-844 [Conf]
  212. Tobi Delbrück, Patrick Lichtsteiner
    Fast sensory motor control based on event-based hybrid neuromorphic-procedural system. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:845-848 [Conf]
  213. Eugenio Culurciello, Joon Hyuk Park, Andreas Savvides
    Address-Event Video Streaming over Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:849-852 [Conf]
  214. Matthias Oster, Rodney J. Douglas, Shih-Chii Liu
    Quantifying Input and Output Spike Statistics of a Winner-Take-All Network in a Vision System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:853-856 [Conf]
  215. Hans Kristian Otnes Berge, Philipp Häfliger
    High-Speed Serial AER on FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:857-860 [Conf]
  216. Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
    Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:861-864 [Conf]
  217. Amit Kedia, Resve Saleh
    Power Reduction of On-Chip Serial Links. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:865-868 [Conf]
  218. Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu
    Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:869-872 [Conf]
  219. Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
    Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:873-876 [Conf]
  220. Atanu Chattopadhyay, Zeljko Zilic
    Reconfigurable Clock Distribution Circuitry. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:877-880 [Conf]
  221. José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:881-884 [Conf]
  222. Abinash Roy, Masud H. Chowdhury
    Global Interconnect Optimization in the Presence of On-chip Inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:885-888 [Conf]
  223. Hirokazu Tohya, Noritaka Toya
    A Novel Design Methodology of the On-Chip Power Distribution Network Enhancing the Performance and Suppressing EMI of the SoC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:889-892 [Conf]
  224. Javier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta
    Asymmetric clock driver for improved power and noise performances. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:893-896 [Conf]
  225. Mosin Mondal, Sami Kirolos, Yehia Massoud
    Estimation of Capacitive Crosstalk-Induced Short-Circuit Energy. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:897-900 [Conf]
  226. Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko
    A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:901-904 [Conf]
  227. Jaehyun Baek, Myung Hoon Sunwoo
    Simplified Degree Computationless Modified Euclid's Algorithm and its Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:905-908 [Conf]
  228. Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel
    Towards Gb/s turbo decoding of product code onto an FPGA device. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:909-912 [Conf]
  229. Tzu-Chieh Kuo, Alan N. Willson Jr.
    Low-latency Memory-efficient 150-Mbps Turbo FEC Encoder and Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:913-916 [Conf]
  230. Zhiqiang Cui, Zhongfeng Wang
    Efficient Message Passing Architecture for High Throughput LDPC Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:917-920 [Conf]
  231. Kofi M. Odame, Paul E. Hasler
    An Efficient Oscillator Design Based on OTA Nonlinearity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:921-924 [Conf]
  232. Manuel Dominguez, Joan Pons, Jordi Ricart
    Application of Pulsed Digital Oscillators in 'reverse mode' to eliminate undesired vibrations in high-Q MEMS resonators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:925-928 [Conf]
  233. Junhong Zhao, Chunyan Wang
    CMOS Current-controlled Oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:929-932 [Conf]
  234. Mostafa Savadi Oskooei, Ali Afzali-Kusha, Seyed Mojtaba Atarodi
    A High-Speed and Low-Power Voltage Controlled Oscillator in 0.18-µm CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:933-936 [Conf]
  235. Shaohua Wang, Jinguo Quan, Rong Luo, Hao Cheng, Huazhong Yang
    A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor Pairs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:937-940 [Conf]
  236. Ivan Padilla, Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín
    Highly Linear V/I Converter with Programmable Current Mirrors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:941-944 [Conf]
  237. Hayg Dabag, Dongwon Seo, Manu Mishra, Josef Hausner
    Electrical Stress-free High Gain and High Swing Analog Buffer Using an Adaptive Biasing Scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:945-948 [Conf]
  238. Tiejun Cao, Hung P. Hoang, Beth O. Woods, H. Alan Mantooth
    A SiGe BiCMOS Variable Gain Amplifier for Cryogenic Temperature Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:949-952 [Conf]
  239. Albert Chow, Hae-Seung Lee
    Transient Noise Analysis for Comparator-Based Switched-Capacitor Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:953-956 [Conf]
  240. Arindam Basu, Paul E. Hasler
    A Fully Integrated Architecture for Fast Programming of Floating Gates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:957-960 [Conf]
  241. Bo Geng, Hong Lu, Xiangyang Xue
    Incremetal Spatio-Temporal Feature Extraction and Retrieval for Large Video Database. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:961-964 [Conf]
  242. Cenk Demiroglu, David V. Anderson, Mark A. Clements
    A Missing Data-based Feature Fusion Strategy for Noise-Robust Automatic Speech Recognition Using Noisy Sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:965-968 [Conf]
  243. Ming-Hsu Cheng, Meng-Fen Ho, Chung-Lin Huang
    Gait Analysis for Human Identification through Manifold Learning and HMM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:969-972 [Conf]
  244. Kwanwoong Song, Taeyoung Chung, Chang-Su Kim, Young O. Park, Yongdeok Kim, Younghun Joo, Yunje Oh
    Efficient Multi-Hypothesis Error Concealment Technique for H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:973-976 [Conf]
  245. Yifeng He, Ivan Lee, Ling Guan
    Optimized multi-path routing using dual decomposition for wireless video streaming. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:977-980 [Conf]
  246. Dionisis Athanasopoulos, Thanos Stouraitis
    Content-Adaptive Wavelet-Based Scalable Video Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:981-984 [Conf]
  247. Shing-Chow Chan, Zhi-Feng Gan, Heung-Yeung Shum
    An Object-based Approach to Plenoptic Video Processing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:985-988 [Conf]
  248. Quqing Chen, Zhengang Nie, Zhibo Chen, Xiaodong Gu, Guoping Qiu, Charles Wang
    A Human Vision System based Flash Picture Coding Method for Video Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:989-992 [Conf]
  249. Jong Dae Oh, Siwei Ma, C. C. Jay Kuo
    Disparity Estimation and Virtual View Synthesis from Stereo Video. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:993-996 [Conf]
  250. Yanwei Liu, Qingming Huang, Debin Zhao, Wen Gao
    Low-delay View Random Access for Multi-view Video Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:997-1000 [Conf]
  251. Pei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Shao-Yi Chien, Tung-Chien Chen, Liang-Gee Chen
    System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1001-1004 [Conf]
  252. Huanxin Guan, Huaguang Zhang, Zhanshan Wang, Derong Liu
    Global Asymptotic Stability of Recurrent Neural Networks with Time Varying Delays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1005-1008 [Conf]
  253. Mohammed A. Hasan
    Upper-Triangulization of Non-Symmetric Matrices Using Sanger's Type Learning Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1009-1012 [Conf]
  254. Aderinto J. Ogunniyi, Stanley L. Henriquez, Caroline W. Karangu, Corey Dickens, Carl White
    Accurate Modeling of Drain Current Derivatives of MESFET/HEMT Devices for Intermodulation Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1013-1016 [Conf]
  255. Jie Yuan, Ning Song, Nabil Farhat, Jan Van der Spiegel
    Cort-X II: low power element design of a large-scale spatio-temporal pattern clustering system. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1017-1020 [Conf]
  256. Giuseppe Acciani, Gioacchino Brunetti, Girolamo Fornarelli
    Automatic Detection of Solder Joint Defects on Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1021-1024 [Conf]
  257. Tsukasa Sone, Toshinori Yamada
    Minimum-Cost Load Balancing Document Distribution in Distributed Web Server Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1025-1028 [Conf]
  258. Ming Cao, Chai Wah Wu
    Topology design for fast convergence of network consensus algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1029-1032 [Conf]
  259. Christopher Jenkins, Jayawant Kakade, Dimitri Kagaris
    Cellular Automata with Large Channel Separations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1033-1036 [Conf]
  260. Awni Itradat, M. Omair Ahmad, Ali Shatnawi
    Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1037-1040 [Conf]
  261. Shyam Subramanian, David V. Anderson
    2-MITE Product-of-Power-Law Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1041-1044 [Conf]
  262. Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara
    DTS: A Tree Based Representation for 3D-Block Packing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1045-1048 [Conf]
  263. Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu
    Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1049-1052 [Conf]
  264. Shilpa Bhoj, Dinesh Bhatia
    Thermal Modeling and Temperature Driven Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1053-1056 [Conf]
  265. Laleh Behjat, Jianhua Li, L. Rakai, Jie Huang
    Two Clustering Preprocessing Techniques for Large-Scale Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1057-1060 [Conf]
  266. K. Duraisami, Prassanna Sithambaram, A. Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino
    Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1061-1064 [Conf]
  267. A. Shahabi, N. Honarmand, Zainalabedin Navabi
    Programmable Routing Tables for Degradable Torus-Based Networks on Chips. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1065-1068 [Conf]
  268. Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu
    A Study on Impact of Leakage Current on Dynamic Power. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1069-1072 [Conf]
  269. Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
    Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1073-1076 [Conf]
  270. Xinjie Wei, Yici Cai, Xianlong Hong
    Effective Acceleration of Iterative Slack Distribution Process. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1077-1080 [Conf]
  271. Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie
    Design and Synthesis of a Three Input Flagged Prefix Adder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1081-1084 [Conf]
  272. Himanshu Thapliyal, A. Prasad Vinod
    Designing Efficient Online Testable Reversible Adders With New Reversible Gate. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1085-1088 [Conf]
  273. John Moskal, Erdal Oruklu, Jafar Saniie
    Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1089-1092 [Conf]
  274. Jong-Suk Lee, Dong Sam Ha
    High Speed 1-bit Bypass Adder Design for Low Precision Additions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1093-1096 [Conf]
  275. Oscar Gustafsson
    A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1097-1100 [Conf]
  276. Hugo Hedberg, Fredrik Kristensen, Viktor Öwall
    Implementation of a Labeling Algorithm based on Contour Tracing with Feature Extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1101-1104 [Conf]
  277. Chia-Liang Tsai, Shao-Yi Chien
    Flexible and Cost Effective Transport Stream Processor for DTV. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1105-1108 [Conf]
  278. Muhammad Bilal, Shahid Masud
    Efficient Color Space Conversion using Custom Instruction in a RISC Processor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1109-1112 [Conf]
  279. Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, Weber Chien
    A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1113-1116 [Conf]
  280. Ullas Pazhayaveetil, Dhruba Chandra, Paul Franzon
    Flexible Low Power Probability Density Estimation Unit For Speech Recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1117-1120 [Conf]
  281. Ming-Dou Ker, Hung-Tai Liao
    Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1121-1124 [Conf]
  282. Boyan Semerdjiev, Dimitrios Velenis
    Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1125-1128 [Conf]
  283. Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
    Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1129-1132 [Conf]
  284. Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
    Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1133-1136 [Conf]
  285. Ming-Hung Chang, Zong-Xi Yang, Wei Hwang
    A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1137-1140 [Conf]
  286. Vishwanadh Tirumalashetty, Hamid Mahmoodi
    Clock Gating and Negative Edge Triggering for Energy Recovery Clock. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1141-1144 [Conf]
  287. Yaseer A. Durrani, Ana Abril, Teresa Riesgo
    Efficient Power Macromodeling Technique for IP-Based Digital System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1145-1148 [Conf]
  288. Yong-Bin Kim, Kyung Ki Kim, James T. Doyle
    A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1149-1152 [Conf]
  289. H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A. Yakovlev
    Impact of strain on the design of low-power high-speed circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1153-1156 [Conf]
  290. Lih-Yih Chiou, Shien-Chun Lou
    An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1157-1160 [Conf]
  291. Kyung Ki Kim, Yong-Bin Kim
    Optimal Body Biasing for Minimum Leakage Power in Standby Mode. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1161-1164 [Conf]
  292. Xiaodong Zhang, Magdy Bayoumi
    A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1165-1168 [Conf]
  293. Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
    A Low Energy FFT/IFFT Processor for Hearing Aids. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1169-1172 [Conf]
  294. Bo Fu, Paul Ampadu
    Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1173-1176 [Conf]
  295. Péter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska
    High performance processor array for image processing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1177-1180 [Conf]
  296. Poramate Manoonpong, Tao Geng, Bernd Porr, Florentin Wörgötter
    The RunBot Architecture for Adaptive, Fast, Dynamic Walking. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1181-1184 [Conf]
  297. Yu M. Chi, Paul Carpenter, Kent Colling, Gert Cauwenberghs, Ralph Etienne-Cummings
    ISCAS Special Session Demo: Wireless Video Sensor for Ad-hoc Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1185- [Conf]
  298. John V. Arthur, Kwabena Boahen
    Silicon Neurons that Inhibit to Synchronize. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1186- [Conf]
  299. Christopher M. Twigg, Paul E. Hasler, I. Faik Baskaya
    A Self-Contained Large-Scale FPAA Development Platform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1187-1191 [Conf]
  300. Alejandro Linares-Barranco, F. Gomez-Rodriguez, A. Jiménez-Fernandez, Tobi Delbrück, P. Lichtensteiner
    Using FPGA for visuo-motor control with a silicon retina and a humanoid robot. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1192-1195 [Conf]
  301. Christoph Posch, Michael Hofstatter, Martin Litzenberger, Daniel Matolin, N. Donath, P. Schon, H. Garn
    Wide dynamic range, high-speed machine vision with a 2×256 pixel temporal contrast vision sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1196-1199 [Conf]
  302. Pierre-François Ruedi, Eric Grenet, Felix Lustenberger
    Battery powered high dynamic range vision system. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1200- [Conf]
  303. F. Gomez-Rodriguez, Alejandro Linares-Barranco, L. Miro-Amarante, Shih-Chii Liu, André van Schaik, Ralph Etienne-Cummings, M. Anthony Lewis
    AER Auditory Filtering and CPG for Robot Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1201-1204 [Conf]
  304. Pujitha Weerakoon, Kate Klemic, Fred J. Sigworth, Eugenio Culurciello
    An Integrated Patch-Clamp Amplifier for High-Density Whole-Cell Recordings. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1205-1208 [Conf]
  305. Felix Lustenberger, David Beyeler, Edo Franzi, Peter Seitz, Thierry Zamofing
    A Universal Method for Hierarchical Object Recognition based on Low-Power Vision Sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1209- [Conf]
  306. Hakon A. Hjortland, Dag T. Wisland, Tor Sverre Lande, Claus Limbodal, Kjetil Meisal
    Thresholded samplers for UWB impulse radar. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1210-1213 [Conf]
  307. Amanda Jimenez-Marrufo, Ainhoa Mendizabal, Sergio Morillas-Castillo, Rafael Domínguez-Castro, Servando Espejo-Meana, Rafael Romay-Juarez, Ángel Rodríguez-Vázquez
    Data Matrix Code Recognition Using the Eye-RIS Vision System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1214- [Conf]
  308. Xicai Yue, Emmanuel M. Drakakis, Hua Ye, Mayasari Lim, A. Mantalaris, Nicki Panoskaltsis, Anna Radomska, Chris Toumazou, T. Cass
    An On-line, Multi-Parametric, Multi-Channel Physicochemical Monitoring Platform for Stem Cell Culture Bioprocessing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1215-1218 [Conf]
  309. Julius Georgiou, Timothy G. Constandinou, Chris Toumazou
    A Micropower Cochlear Prosthesis System Demonstrator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1219- [Conf]
  310. Yifeng Qiu, Wael M. Badawy, Robert Turney
    A Prototyping Co-design Platform with A Simplified Architecture for Video Codec Implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1220-1224 [Conf]
  311. Yongjian Tang, Hans Hegt, Arthur H. M. van Roermund, Konstantinos Doris, Joost Briaire
    Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1225-1228 [Conf]
  312. Andreas Tritschler
    A Continuous Time Analog-to-Digital Converter With 90µW and 1.8µV/LSB Based on Differential Ring Oscillator Structures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1229-1232 [Conf]
  313. Anand Meruva, Bahar Jalali Farahani
    Digital Background Calibration of Higher Order Nonlinearities in Pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1233-1236 [Conf]
  314. John A. McNeill, Sanjeev Goluguri, Abhilash Nair
    "Split-ADC" Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1237-1240 [Conf]
  315. Pingli Huang, Yun Chiu
    A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1241-1244 [Conf]
  316. Peter R. Kinget
    Device Mismatch: An Analog Design Perspective. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1245-1248 [Conf]
  317. Michael Fulde, Doris Schmitt-Landsiedel, Gerhard Knoblinger
    Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1249-1252 [Conf]
  318. Khurram Waheed, Robert B. Staszewski
    Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1253-1256 [Conf]
  319. Ronald Carlsten, Jeremy Ralston-Good, Douglas Goodman
    An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1257-1260 [Conf]
  320. Brian Greskamp, Smruti R. Sarangi, Josep Torrellas
    Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1261-1264 [Conf]
  321. Yun Q. Shi, Chunhua Chen, Wen Chen, Maala P. Kaundinya
    Effect of Recompression on Attacking JPEG Steganographic Schemes An Experimental Study. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1265-1268 [Conf]
  322. Huijuan Yang, Alex C. Kot
    Data Hiding For Binary Images Authentication By Considering A Larger Neighborhood. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1269-1272 [Conf]
  323. Richard Y. M. Li, Oscar C. Au, Carman K. M. Yuk, Shu-Kei Yip, Tai-Wai Chan
    Enhanced Image Trans-coding Using Reversible Data Hiding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1273-1276 [Conf]
  324. Tsung-Huang Chen, Shao-Yi Chien
    Cost Effective Color Filter Array Demosaicking with Chrominance Variance Weighted Interpolation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1277-1280 [Conf]
  325. Carman K. M. Yuk, Oscar C. Au, Richard Y. M. Li, Sui-Yuk Lam
    Color Demosaicking Using Direction Similarity in Color Difference Spaces. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1281-1284 [Conf]
  326. J. Tapson, Ralph Etienne-Cummings
    A Simple Neural Cross-Correlation Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1285-1288 [Conf]
  327. Paul Kucher, Shantanu Chakrabartty
    An Energy-Scalable Margin Propagation-Based Analog VLSI Support Vector Machine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1289-1292 [Conf]
  328. Simone Fiori
    Neural Learning by Retractions on Manifolds. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1293-1296 [Conf]
  329. C. C. Lu, C. Y. Hong, H. Chen
    A Scalable and Programmable Architecture for the Continuous Restricted Boltzmann Machine in VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1297-1300 [Conf]
  330. Terrence S. T. Mak, K. P. Lam, H. S. Ng, G. Rachmuth, C.-S. Poon
    A Current-Mode Analog Circuit for Reinforcement Learning Problems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1301-1304 [Conf]
  331. Yodchanan Wongsawat, Soontorn Oraintara, K. R. Rao
    Reduced Complexity Space-Time-Frequency Model for Multi-Channel EEG and Its Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1305-1308 [Conf]
  332. K. M. Tsui, Zhiguo Zhang, Shing-Chow Chan, Yong Hu, Keith D. K. Luk
    On the Time-frequency Analysis of Trunk Muscles During Sudden Release of Load. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1309-1312 [Conf]
  333. Alexandra Delia Doljanu, Mohamad Sawan
    3D Shape Acquisition System Dedicated to a Visual Intracortical Stimulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1313-1316 [Conf]
  334. Paolo Arena, Maide Bucolo, Luigi Fortuna, Mattia Frasca, Manuela La Rosa, F. Sapuppo, E. Umana, David Shannahoff-Khalsa
    d-infinite Criteria for MEG Characterization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1317-1320 [Conf]
  335. Xiaowen Li, Xiang Xie, Xinkai Chen, GuoLin Li, Li Zhang, Zhihua Wang, Hong Chen
    Design and Implementation of a Low Complexity Near-lossless Image Compression Method for Wireless Endoscopy Capsule System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1321-1324 [Conf]
  336. Ji-Hoon Kim, In-Cheol Park
    Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1325-1328 [Conf]
  337. P. P. Vaidyanathan
    On equalization of channels with ZP precoders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1329-1332 [Conf]
  338. Suchada Sitjongsataporn, Peerapol Yuvapoositanon
    An Adaptive Step-size Order Statistic Time Domain Equaliser for Discrete Multitone Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1333-1336 [Conf]
  339. Dimitrios Katselis, Eleftherios Kofidis, Sergios Theodoridis
    Training-Based Estimation of Correlated MIMO Fading Channels in the Presence of Colored Interference. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1337-1340 [Conf]
  340. Rafiahamed Shaik, Mrityunjoy Chakraborty
    An Efficient Finite Precision Realization of the Adaptive Decision Feedback Equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1341-1344 [Conf]
  341. James Ayers, Kartikeya Mayaram, Terri S. Fiez
    Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1345-1348 [Conf]
  342. Lu Chao, Chi-Ying Tsui, Wing-Hung Ki
    A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1349-1352 [Conf]
  343. Hui Shao, Chi-Ying Tsui, Wing-Hung Ki
    An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1353-1356 [Conf]
  344. Yi Wang, Dan Zhao
    Design and Implementation of Routing Scheme for Wireless Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1357-1360 [Conf]
  345. Stig Stoa, Ilangko Balasingham, Tor A. Ramstad
    Data Throughput Optimization in the IEEE 802.15.4 Medical Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1361-1364 [Conf]
  346. Amit Kumar Gupta, Saeid Nooshabadi, David Taubman
    Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 Encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1365-1368 [Conf]
  347. Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franzon
    Hardware Architecture of a Parallel Pattern Matching Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1369-1372 [Conf]
  348. Roberto Muscedere
    A Hardware Efficient Very Large Bit Word Binary to Double Base Number System Converter for Encryption Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1373-1376 [Conf]
  349. Rahul Jain, Preeti Ranjan Panda
    An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1377-1380 [Conf]
  350. Wei-Feng He, Zhi-Gang Mao
    An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1381-1384 [Conf]
  351. Ahmed Shebaita, Yehea I. Ismail
    Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1385-1388 [Conf]
  352. Zhiyu Liu, Volkan Kursun
    Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1389-1392 [Conf]
  353. Baozhen Yu, Michael L. Bushnell
    Power Grid Analysis of Dynamic Power Cutoff Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1393-1396 [Conf]
  354. Sherif A. Tawfik, Volkan Kursun
    Multi-Vth Level Conversion Circuits for Multi-VDD Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1397-1400 [Conf]
  355. Saihua Lin, Huazhong Yang, Rong Luo
    A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1401-1404 [Conf]
  356. Rachit Agarwal, Emanuel M. Popovici, Brendan O'Flynn, Michael E. O'Sullivan
    A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1405-1408 [Conf]
  357. Jun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen
    Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1409-1412 [Conf]
  358. Xinmiao Zhang, Jiangli Zhu
    Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1413-1416 [Conf]
  359. S. Haene, Andreas Burg, P. Luethi, Norbert Felber, Wolfgang Fichtner
    FFT Processor for OFDM Channel Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1417-1420 [Conf]
  360. P. Luethi, Andreas Burg, S. Haene, David Perels, Norbert Felber, Wolfgang Fichtner
    VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1421-1424 [Conf]
  361. Stefano Vitali, Giampaolo Cimatti, Riccardo Rovatti, Gianluca Setti
    Algorithmic ADC Offset Compensation by Non-White Data Chopping. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1425-1428 [Conf]
  362. Xi Chen, Siu Chung Wong, Chi K. Michael Tse, Ljiljana Trajkovic
    Stability Analysis of RED Gateway with Multiple TCP Reno Connections. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1429-1432 [Conf]
  363. Shintaro Arai, Yoshifumi Nishio
    Noncoherent Correlation-Based Communication Systems Choosing Different Chaotic Maps. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1433-1436 [Conf]
  364. Fabio Pareschi, Riccardo Rovatti, Gianluca Setti
    Second-level NIST Randomness Tests for Improving Test Reliability. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1437-1440 [Conf]
  365. Luca Antonio De Michele, Giampaolo Cimatti, Riccardo Rovatti, Gianluca Setti
    Joint Design of a DS-UWB Modulator and Chaos-Based Spreading Sequences for Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1441-1444 [Conf]
  366. Wesley A. Gee, Phillip E. Allen
    CMOS Integrated LC RF Bandpass Filter with Transformer-Coupled Q-Enhancement and Optimized Linearity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1445-1448 [Conf]
  367. Miguel A. Martins, Jorge R. Fernandes, Manuel M. Silva
    Techniques for Dual-Band LNA Design using Cascode Switching and Inductor Magnetic Coupling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1449-1452 [Conf]
  368. Md. Mahbub Reja, C. Sellathamby, Igor M. Filanovsky
    A New CMOS 3.1-11.7 GHz Low Power LNA for Ultra-Wideband Wireless Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1453-1456 [Conf]
  369. Shaikh K. Alam, Joanne DeGroat
    A CMOS Variable Gain Front-end for a WCDMA Receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1457-1460 [Conf]
  370. Luís Bica Oliveira, Jorge R. Fernandes, Manuel M. Silva, Igor M. Filanovsky, Chris J. M. Verhoeven
    Experimental Evaluation of Phase-Noise and Quadrature Error in a CMOS 2.4 GHz Relaxation Oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1461-1464 [Conf]
  371. Georgi I. Radulov, Patrick J. Quinn, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund
    Parallel current-steering D/A Converters for Flexibility and Smartness. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1465-1468 [Conf]
  372. Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio
    A 12-bit Current-Steering DAC with Calibration by Combination Selection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1469-1472 [Conf]
  373. Babak Nejati, Larry Larson
    Power/Area Trade-Offs in Low-Power/Low-Area Unary-R-2R CMOS Digital-to-Analog Converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1473-1476 [Conf]
  374. B. Catteau, Pieter Rombouts, Ludo Weyten
    A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1477-1480 [Conf]
  375. Behnam Sedighi, Mehrdad Sharif Bakhtiar
    An 8-bit 300MS/s Switched-Current Pipeline ADC in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1481-1484 [Conf]
  376. Min Ma, Roni Khazaka
    Multi-level Order Reduction with Nonlinear Port Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1485-1488 [Conf]
  377. Yuya Nakazono, Hideki Asai
    Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1489-1492 [Conf]
  378. Ege Engin, Krishna Bharath, Madhavan Swaminathan
    Analysis for Signal and Power Integrity Using the Multilayered Finite Difference Method. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1493-1496 [Conf]
  379. Taha Amiralli, Anestis Dounavis
    Macromodeling for Nonlinear Distributed Interconnect Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1497-1500 [Conf]
  380. Wendemagegnehu T. Beyene
    Low-Order Rational Approximation of Interconnects Using Neural-Network Based Pole-Clustering Techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1501-1504 [Conf]
  381. Naeem Ramzan, Shuai Wan, Ebroul Izquierdo
    An Efficient Joint Source-Channel Coding for Wavelet Based Scalable Video. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1505-1508 [Conf]
  382. Wen-Nung Lie, Han-Ching Yeh, Zhi-Wei Gao, Ping-Chang Jui
    Error-Resilience Transcoding of H.264/AVC Compressed Videos. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1509-1512 [Conf]
  383. Lei Yao, Lei Cao
    UEP for Progressive Image Transmission with GA-based Optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1513-1516 [Conf]
  384. David Levine, William E. Lynch, Tho Le-Ngoc
    Iterative Joint Source-Channel Decoding of H.264 Compressed Video. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1517-1520 [Conf]
  385. Davy De Schrijver, Wesley De Neve, Koen De Wolf, Peter Lambert, Davy Van Deursen, Rik Van de Walle
    XML-driven Exploitation of Combined Scalability in Scalable H.264/AVC Bitstreams. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1521-1524 [Conf]
  386. Alex Russell, Garrick Orchard, Ralph Etienne-Cummings
    Configuring of Spiking Central Pattern Generator Networks for Bipedal Walking Using Genetic Algorthms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1525-1528 [Conf]
  387. Ismail Uysal, Harsha Sathyendra, John G. Harris
    Spike-Based Feature Extraction for Noise Robust Speech Recognition Using Phase Synchrony Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1529-1532 [Conf]
  388. Haruna Matsushita, Yoshifumi Nishio
    Self-Organizing Map Considering False Neighboring Neuron. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1533-1536 [Conf]
  389. L. Miro-Amarante, A. Jiménez-Fernandez, Alejandro Linares-Barranco, F. Gomez-Rodriguez, R. Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona
    LVDS Serial AER Link performance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1537-1540 [Conf]
  390. Paolo Checco, Mario Biey, Marco Righero, Ljupco Kocarev
    Synchronization and Bifurcations in Networks of Coupled Hindmarsh-Rose Neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1541-1544 [Conf]
  391. Olivier Valorge, Benoit Gosselin, Louis-Francois Tanguay, Mohamad Sawan
    Electromagnetic Compatibility Modeling in Low-Noise Medical Sensor Interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1545-1548 [Conf]
  392. Andrea Fantini, Alessandro Cabrini, Guido Torelli
    Impact of Control Signal Non-Idealties on Two-Phase Charge Pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1549-1552 [Conf]
  393. Maneesha Yellepeddi, Kartikeya Mayaram
    Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1553-1556 [Conf]
  394. Paul E. Hasler, Arindam Basu, Sctt Kozil
    Above Threshold pFET InjectionModeling intended for ProgrammingFloating-Gate Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1557-1560 [Conf]
  395. Bernabé Linares-Barranco, Teresa Serrano-Gotarredona
    A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1561-1564 [Conf]
  396. Guichang Zhong, Alan N. Willson Jr.
    An Energy-efficient Reconfigurable Viterbi Decoder on a Programmable Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1565-1568 [Conf]
  397. Guo-An Jian, Chih-Da Chien, Jiun-In Guo
    A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1569-1572 [Conf]
  398. Zhenmin Li, Taewhan Kim
    Address Code Optimization Exploiting Code Scheduling in DSP Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1573-1576 [Conf]
  399. Xiaoxiang Gong, John G. Harris
    A Precompensation Algorithm for PWM-Based Digital Audio Amplifiers for Portable Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1577-1580 [Conf]
  400. Chun-Yat Ma, Tai-Chiu Hsung, Daniel Pak-Kong Lun, K. C. Ho, H. K. Kwan
    Denoising for Generalized Sidelobe Canceller. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1581-1584 [Conf]
  401. Adam S. W. Man, Edward S. Zhang, H. T. Chan, Vincent K. N. Lau, C. Y. Tsui, Howard C. Luong
    Design and Implementation of a Low-power Baseband-system for RFID Tag. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1585-1588 [Conf]
  402. Andrea Ricci, Ilaria De Munari
    Enabling Pervasive Sensing with RFID: An Ultra Low-Power Digital Core for UHF Transponders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1589-1592 [Conf]
  403. Majid Baghaei Nejad, Zhuo Zou, Hannu Tenhunen, Li-Rong Zheng
    A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1593-1596 [Conf]
  404. Jinseok Lee, Kyoung-Su Park, Sangjin Hong, We-Duke Cho
    Object Tracking Based on RFID Coverage Visual Compensation in Wireless Sensor Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1597-1600 [Conf]
  405. Meng-Lin Hsia, Oscal T.-C. Chen
    Low-Complexity Encryption Using Redundant Bits and Adaptive Frequency Rates in RFID. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1601-1604 [Conf]
  406. Genhua Jin, Jin-Su Jung, Hyuk-Jae Lee
    An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1605-1608 [Conf]
  407. K. Gaedke, M. Borsum, M. Georgi, A. Kluger, J.-P. Le Glanic, P. Bernard
    Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1609-1612 [Conf]
  408. Woong Hwangbo, Jaemoon Kim, Chong-Min Kyung
    A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1613-1616 [Conf]
  409. Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
    MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1617-1620 [Conf]
  410. Yongje Lee, Chae-Eun Rhee, Hyuk-Jae Lee
    A New Frame Recompression Algorithm Integrated with H.264 Video Compression. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1621-1624 [Conf]
  411. Peiyi Zhao, Jason McNeely, Magdy A. Bayoumi, Golconda Pradeep Kumar, Weidong Kuang
    A Low Power Domino with Differential-Controlled-Keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1625-1628 [Conf]
  412. Nainesh Agarwal, Nikitas J. Dimopoulos
    Towards Automated Power Gating of Registers using CoDeL. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1629-1632 [Conf]
  413. Enrico Dallago, Daniele Miatton, G. Venchi, Giovanni Frattini, Giulio Ricotti
    Self-Supplied Integrable Active High-Efficiency AC-DC Converter for Piezoelectric Energy Scavenging Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1633-1636 [Conf]
  414. Wei-Chih Hsieh, Wei Hwang
    Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1637-1640 [Conf]
  415. Ahmed Sayed, Hussain Al-Asaad
    A New Statistical Approach for Glitch Estimation in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1641-1644 [Conf]
  416. Kiran K. Gunnam, Gwan Choi, Weihuang Wang, Mark B. Yeary
    Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1645-1648 [Conf]
  417. Yi-Hsing Chien, Mong-Kai Ku
    A High Throughput H-QC LDPC Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1649-1652 [Conf]
  418. Zhiyong He, Sébastien Roy, Paul Fortier
    FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1653-1656 [Conf]
  419. Emil Matús, Marcos B. S. Tavares, Marcel Bimberg, Gerhard Fettweis
    Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1657-1660 [Conf]
  420. Abu Baker, Soumik Ghosh, Ashok Kumar, Magdy A. Bayoumi, Rafic A. Ayoubi
    Design and Realization of Analog Phi-Function for LDPC Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1661-1664 [Conf]
  421. Martin Hasler, Igor Belykh, Vladimir Belykh
    Classes of stochastically switched (blinking) systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1665-1668 [Conf]
  422. Paolo Checco, Mario Biey, Ljupco Kocarev
    Synchronization in Complex Hybrid Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1669-1672 [Conf]
  423. Arindam Basu, Kofi M. Odame, Paul E. Hasler
    Dynamics of a Logarithmic Transimpedance Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1673-1676 [Conf]
  424. Zbigniew Galias, Xinghuo Yu
    Equivalence of two discretization schemes in a simple sliding mode control system. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1677-1680 [Conf]
  425. Jiuchao Feng, Hongjuan Fan, Chi K. Michael Tse
    Convergence Analysis of the Unscented Kalman Filter for Filtering Noisy Chaotic Signals. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1681-1684 [Conf]
  426. Seung-Min Oh, Kyoung-Seok Park, Hyun-Hwan Yoo, Yoo-Sam Na, Taek-Soo Kim
    A Design of DC Offset Canceller using Parallel Compensation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1685-1688 [Conf]
  427. Jian-Hong Fang, Norman M. Filiol, Tom A. D. Riley, Miles A. Copeland
    A Second Order Delta-Sigma Frequency Discriminator with Fractional-N Divider and Multi-Bit Quantizer. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1689-1692 [Conf]
  428. Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli
    A Power Optimized Base-Band Circuitry for the Low-IF Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1693-1696 [Conf]
  429. Bob Stengel, Said Rami
    A 90nm Quadrature Generator with Frequency Extension up to 4GHz. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1697-1700 [Conf]
  430. Malihe Zarre Dooghabadi, Sasan Naseh
    A New Quadrature LC-Oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1701-1704 [Conf]
  431. Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
    Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1705-1708 [Conf]
  432. Cheng Chen, Jiren Yuan
    A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1709-1712 [Conf]
  433. Jere A. M. Jarvinen, Mikko Saukoski, Kari Halonen
    A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1713-1716 [Conf]
  434. Devrim Yilmaz Aksin, Mohammad A. Al-Shyoukh, Franco Maloberti
    An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1717-1720 [Conf]
  435. Lei Wang, Junyan Ren, Wenjing Yin, Tingqian Chen, Jun Xu
    A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1721-1724 [Conf]
  436. Andrew G. Dempster
    Satellite Navigation: New Signals, New Challenges. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1725-1728 [Conf]
  437. Ediz Çetin, Izzet Kale, Richard C. S. Morling
    Analysis and Compensation of RF Impairments for Next Generation Multimode GNSS Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1729-1732 [Conf]
  438. Gianmarco Girau, Andrea Tomatis, Fabio Dovis, Paolo Mulassano
    Efficient Software Defined Radio Implementations of GNSS Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1733-1736 [Conf]
  439. Olivier Julien, Gérard Lachapelle, M. Elizabeth Cannon
    Galileo L1 Civil Receiver Tracking Loops' Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1737-1741 [Conf]
  440. Deok Won Lim, Sang Jeong Lee, Deuk Jae Cho
    Design of an Assisted GPS Receiver and its Performance Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1742-1745 [Conf]
  441. Y. Liu, Y. C. Soh, Z. G. Li
    Rate Control for Spatial/CGS Scalable Extension of H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1746-1750 [Conf]
  442. Fengling Li, Nam Ling, Stephen A. Chiappari
    Multi-Stage MCTF Coding Efficiency Analysis with Directed-Tree Model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1751-1754 [Conf]
  443. Yu Liu, Feng Wu, King Ngi Ngan
    3D Object-based Scalable Wavelet Video Coding with Boundary Effect Suppression. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1755-1758 [Conf]
  444. Wei Yao, Zhengguo Li, Susanto Rahardja
    Balanced Inter-Layer Prediction for Combined Coarse Granular Scalability and Spatial Scalability. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1759-1762 [Conf]
  445. Ruiqin Xiong, Jizheng Xu, Feng Wu, Shipeng Li
    Macroblock-Based Adaptive In-Scale Prediction for Scalable Video Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1763-1766 [Conf]
  446. Shaosheng Zhou, Wei Xing Zheng
    A Study of Delay-Dependent Stabilization for Discrete-Time Systems with Time Delays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1767-1770 [Conf]
  447. Mark D. Skowronski, John G. Harris
    Noise-robust automatic speech recognition using a discriminative echo state network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1771-1774 [Conf]
  448. Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert Cauwenberghs
    Multi-Channel Coherent Detection for Delay-Insensitive Model-Free Adaptive Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1775-1778 [Conf]
  449. Mohammed A. Hasan
    Generalizations of Oja's Learning Rule to Non-Symmetric Matrices. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1779-1782 [Conf]
  450. Yoshifumi Tada, Yoko Uwate, Yoshifumi Nishio
    Effective Search with Hopping Chaos for Hopfield Neural Networks Solving QAP. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1783-1786 [Conf]
  451. Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
    A Structured ASIC Design Approach Using Pass Transistor Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1787-1790 [Conf]
  452. Haider Ali, Bashir M. Al-Hashimi
    Architecture Level Power-Performance Tradeoffs for Pipelined Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1791-1794 [Conf]
  453. Yukihide Kohira, Atsushi Takahashi
    A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1795-1798 [Conf]
  454. Renato Rimolo-Donadio, Antonio J. Acosta, Wolfgang H. Krautschneider
    Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1799-1802 [Conf]
  455. Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao
    Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1803-1806 [Conf]
  456. Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh
    DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1807-1810 [Conf]
  457. Salvatore Caporale, Luca De Marchi, Nicolo Speciale
    An Accurate Algorithm for Fast Frequency Warping. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1811-1814 [Conf]
  458. S. C. Chan, Z. G. Zhang, K. M. Tsui
    Minimum Variance Spectral Estimation-Based Time Frequency Analysis for Nonstationary Time-Series. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1815-1818 [Conf]
  459. Hamid Hassanpour
    Improved SVD-Based Technique for Enhancing the Time-Frequency Representation of Signals. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1819-1822 [Conf]
  460. Fabio P. Freeland, Luiz W. P. Biscainho, Paulo S. R. Diniz
    HRTF Interpolation Through Direct Angular Parameterization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1823-1826 [Conf]
  461. Máire McLoone, Matthew J. B. Robshaw
    New Architectures for Low-Cost Public Key Cryptography on RFID Tags. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1827-1830 [Conf]
  462. Lejla Batina, Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede
    Public-Key Cryptography on the Top of a Needle. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1831-1834 [Conf]
  463. Franz Fürbass, Johannes Wolkerstorfer
    ECC Processor with Low Die Size for RFID Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1835-1838 [Conf]
  464. Martin Feldhofer, Johannes Wolkerstorfer
    Strong Crypto for RFID Tags - A Comparison of Low-Power Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1839-1842 [Conf]
  465. Axel Poschmann, Gregor Leander, Kai Schramm, Christof Paar
    New Light-Weight Crypto Algorithms for RFID. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1843-1846 [Conf]
  466. Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
    SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1847-1850 [Conf]
  467. Hua Li, Jianzhou Li
    A New Compact Architecture for AES with Optimized ShiftRows Operation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1851-1854 [Conf]
  468. Daesun Oh, Keshab K. Parhi
    Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1855-1858 [Conf]
  469. Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
    A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1859-1862 [Conf]
  470. Akashi Satoh
    High-Speed Parallel Hardware Architecture for Galois Counter Mode. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1863-1866 [Conf]
  471. Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran
    Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1867-1870 [Conf]
  472. Stéphane Badel, Yusuf Leblebici
    Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1871-1874 [Conf]
  473. Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan
    Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1875-1878 [Conf]
  474. Riaz Naseer, Younes Boulghassoul, Jeff Draper, Sandeepan DasGupta, Art Witulski
    Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1879-1882 [Conf]
  475. Yufeng Xie, Leibo Liu, Rui Dai, Shaojun Wei
    Battery-Aware Variable Voltage Scheduling on Real-Time Multiprocessor Platforms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1883-1886 [Conf]
  476. You Zheng, Carlos E. Saavedra
    A Microwave OTA Using a Feedforward-Regulated Cascode Topology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1887-1890 [Conf]
  477. Miguel Ângelo M. Madureira, Daniel Fonseca, Adolfo V. T. Cartaxo, Paulo M. P. Monteiro, Rui L. Aguiar
    GVD and PMD Compensation Using a Linear Adjustable Filter Prototype in a 40 Gb/s OSSB System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1891-1894 [Conf]
  478. Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
    A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1895-1898 [Conf]
  479. Borching Su, P. P. Vaidyanathan
    On the Persistency of Excitation for Blind Channel Estimation in Cyclic Prefix Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1899-1902 [Conf]
  480. David Perels, Christoph Studer, Wolfgang Fichtner
    Implementation of a Low-Complexity Frame-Start Detection Algorithm for MIMO Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1903-1906 [Conf]
  481. Christian Falconi, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
    Low Voltage CMOS Current and Voltage References without Resistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1907-1910 [Conf]
  482. Juan Pablo Martinez Brito, Sergio Bampi, Hamilton Klimach
    A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1911-1914 [Conf]
  483. Mikko Loikkanen, Juha Kostamovaara
    A Capacitor-Free CMOS Low-Dropout Regulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1915-1918 [Conf]
  484. Jader A. De Lima, Wallace A. Pimenta
    A gm-C Ramp Generator for Voltage Feedforward Control of DC-DC Switching Regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1919-1922 [Conf]
  485. Anna Arbat, Ángel Dieguez, Josep Samitier
    An Improved Temperature Compensation Technique for Current Biasing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1923-1926 [Conf]
  486. H. Gaunholt
    A numerical design approach for single amplifier, Active-RC Butterworth filter of order 5. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1927-1930 [Conf]
  487. Ioannis Sarkas, Dimitrios Mavridis, Michail Papamichail, George Papadopoulos
    Volterra Analysis Using Chebyshev Series. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1931-1934 [Conf]
  488. William H. Kao, Xiaopeng Dong
    Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1935-1938 [Conf]
  489. Tonse Laxminidhi, Shanthi Pavan
    Design Centering High Frequency Integrated Continuous-Time Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1939-1942 [Conf]
  490. Mohammad Danaie, Hamed Aminzadeh, Sasan Naseh
    On the Linearization of MOSFET Capacitors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1943-1946 [Conf]
  491. Weng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins
    A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1947-1950 [Conf]
  492. Pieter Harpe, Athon Zanikopoulos, Hans Hegt, Arthur H. M. van Roermund
    Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1951-1954 [Conf]
  493. Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee
    A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1955-1958 [Conf]
  494. Jason N. Laska, Sami Kirolos, Marco F. Duarte, Tamer Ragheb, Richard G. Baraniuk, Yehia Massoud
    Theory and Implementation of an Analog-to-Information Converter using Random Demodulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1959-1962 [Conf]
  495. Behnam Sedighi, Mehrdad Sharif Bakhtiar
    An 8-bit Switched-Resistor Pipeline ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1963-1966 [Conf]
  496. W. M. Huang, J. P. John, S. Braithwaite, J. Kirchgessner, I. S. Lim, D. Morgan, Y. B. Park, S. Shams, I. To, P. Welch, R. Reuter, H. Li, A. Ghazinour, Peter Wennekers, Yi Yin
    SiGe 77GHz Automotive Radar Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1967-1970 [Conf]
  497. S. P. Voinigescu, S. T. Nicolson, M. Khanpour, K. K. W. Tang, K. H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, G. Eleftheriades, P. Schvan, M. T. Yang
    CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1971-1974 [Conf]
  498. Helen Kim, Sean Duffy, Jeff Herd, Charles Sodini
    SiGe IC- based mm-wave imager. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1975-1978 [Conf]
  499. Eckhard Grass, Frank Herzel, Maxim Piz, Klaus Schmalz, Yaoming Sun, Srdjan Glisic, Milos Krstic, Klaus Tittelbach-Helmrich, Marcus Ehrig, Wolfgang Winkler, Christoph Scheytt, Rolf Kraemer
    60 GHz SiGe-BiCMOS Radio for OFDM Transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1979-1982 [Conf]
  500. Behzad Razavi
    CMOS Transceivers at 60 GHz and Beyond1. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1983-1986 [Conf]
  501. Xianghui Wei, Shen Li, Yang Song, Satoshi Goto
    An Irregular Search Window Reuse Scheme for Motion Estimation in MPEG-2 to H.264 Transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1987-1990 [Conf]
  502. Jun Xin, Jianjun Li, Anthony Vetro, Huifang Sun, Shun-ichi Sekiguchi
    Motion Mapping for MPEG-2 to H.264/AVC Transcoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1991-1994 [Conf]
  503. Yi-Nung Liu, Chi-Sun Tang, Shao-Yi Chien
    Coding Mode Analysis of MPEG-2 to H.264/AVC Transcoding for Digital TV Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1995-1998 [Conf]
  504. Tsung-Han Tsai, Hsueh-Yi Lin, Yu-Xuan Lee, Pin-Hua Chen
    Complexity Reduction of H.263 to H.264 Transcoder with Fast Mode Decision. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1999-2002 [Conf]
  505. Haiyan Shu, King Ngi Ngan
    Quality Enhancement in H.264 Transform Domain Downsizing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2003-2006 [Conf]
  506. David Sander, Marc Dandin, Honghao Ji, Nicole M. Nelson, Pamela Abshire
    Low-noise CMOS Fluorescence Sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2007-2010 [Conf]
  507. Jennifer Blain Christen, Andreas G. Andreou
    Design, Analysis and Implementation of Integrated Micro-Thermal Control Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2011-2014 [Conf]
  508. Jian-Yun Lai, Yan-Ting Chen, Te-Heng Wang, Hong-Si Chang, Jui-Lin Lai
    Biosensor Integrated with Transducer to Detect the Glucose. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2015-2018 [Conf]
  509. Chin-Teng Lin, Li-Wei Ko, Ken-Li Lin, Sheng-Fu Liang, Bor-Chen Kuo, I-Fang Chung, Lan-Da Van
    Classification of Driver's Cognitive Responses Using Nonparametric Single-trial EEG Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2019-2023 [Conf]
  510. Jun Ohta, Takahashi Tokuda, Keiichiro Kagawa, Akihiro Uehara, Yasuo Terasawa, Kazuaki Nakauchi, Takashi Fujikado, Yasuo Tano
    A multi-microchip retinal stimulator for in vitro / in vivo experiments. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2024-2027 [Conf]
  511. Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yi-Wen Wang, Ching-Hwa Cheng
    Noise-Aware Floorplanning for Fast Power Supply Network Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2028-2031 [Conf]
  512. Karthik Krishnamoorthy, Sarat C. Maruvada, Florin Balasa
    Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2032-2035 [Conf]
  513. Renato Fernandes Hentschke, Ricardo Reis
    A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2036-2039 [Conf]
  514. Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai
    Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2040-2043 [Conf]
  515. Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma
    A Fast 3D-BSG Algorithm for 3D Packing Problem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2044-2047 [Conf]
  516. Wu-Sheng Lu, Takao Hinamoto
    Design of FIR Filters with Discrete Coefficients via Polynomial Programming: Towards the Global Solution. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2048-2051 [Conf]
  517. Raija Lehto, Tapio Saramäki, Olli Vainio
    Synthesis of Wideband Linear-Phase FIR Filters with a Piecewise-Polynomial-Sinusoidal Impulse Response. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2052-2055 [Conf]
  518. Chia-Yu Yao, Alan N. Willson Jr.
    The Design of Symmetric Square-Root Pulse-Shaping Filters for Transmitters and Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2056-2059 [Conf]
  519. Pavel Zahradnik, Miroslav Vlcek, Boris Simák
    Analytical Design of an Equiripple DC-Notch FIR Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2060-2063 [Conf]
  520. Xiaoping Lai
    A Sequential Constrained Least-Square Method for Minimax Design of Linear-phase FIR filters with Time-domain Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2064-2067 [Conf]
  521. Rahul Sarpeshkar, Woradorn Wattanapanitch, Benjamin I. Rapoport, Scott K. Arfin, Michael W. Baker, Soumyajit Mandal, Michale S. Fee, Sam Musallam, Richard A. Andersen
    Low-Power Circuits for Brain-Machine Interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2068-2071 [Conf]
  522. F. Mounaim, Mohamad Sawan
    Miniature Implantable System Dedicated to Bi-Channel Selective Neurostimulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2072-2075 [Conf]
  523. Xiao Liu, Andreas Demosthenous, Nick Donaldson
    A Fully Integrated Fail-safe Stimulator Output Stage Dedicated to FES Stimulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2076-2079 [Conf]
  524. Reid R. Harrison
    Designing Efficient Inductive Power Links for Implantable Devices. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2080-2083 [Conf]
  525. Rizwan Bashirullah, John G. Harris, Justin C. Sanchez, Toshikazu Nishida, José Carlos Príncipe
    Florida Wireless Implantable Recording Electrodes (FWIRE) for Brain Machine Interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2084-2087 [Conf]
  526. Sungchung Park, Yun-Young Kim, Jae-Ho Noh, Jun-Jin Kong
    CSI-aided Demapping of Dual-Carrier Modulation for Multiband-OFDM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2088-2091 [Conf]
  527. Wei-Chang Liu, Ting-Chen Wei, Shyh-Jye Jou
    Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2092-2095 [Conf]
  528. Yuping Zhang, Keshab K. Parhi
    Parallel Architecture of List Sphere Decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2096-2099 [Conf]
  529. Qinqin Chen, Zhongfeng Wang, Jun Ma
    FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2100-2103 [Conf]
  530. Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
    VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2104-2107 [Conf]
  531. Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak
    Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2108-2111 [Conf]
  532. Jeabin Lee, Byeong-Gyu Nam, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo
    A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2112-2115 [Conf]
  533. Parth Malani, Prakash Mukre, Qinru Qiu
    Profile-Based Low Power Scheduling for Conditional Task Graph: A Communication Aware Approach. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2116-2119 [Conf]
  534. Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimin Zhang, Jun Wang
    Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2120-2123 [Conf]
  535. Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu
    Quasi-Static Energy Recovery Logic with Single Power-Clock Supply. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2124-2127 [Conf]
  536. Shayan Farahvash, Chee Quek, William Roberts, David Walker, Mohamed Mostafa, Hauw Liem, Robert Koupal
    A Two-port GFSK Direct Modulator for Wideband Applications at 5.8 GHz. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2128-2131 [Conf]
  537. Yikui Dong, Cathy Liu, Freeman Zhong
    Integrated Linear AC-coupling Circuit for DC-Balanced and Non-Balanced Traffics. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2132-2135 [Conf]
  538. Ayman A. Fayed, Mohammed Ismail
    A 3.7mW, 1.6V CMOS Analog Adaptive Equalizer for a 125Mbps Wire-Line Transceiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2136-2139 [Conf]
  539. Andrea Bevilacqua, Christoph Sandner, Andrea Gerosa, Andrea Neviani
    Quadrature VCOs Based on Coupled PLLs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2140-2143 [Conf]
  540. Chanwoo Park, Jinbeom Lee, Younglok Kim
    Modified Reduced Constellation PLL for Higher Order QAM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2144-2147 [Conf]
  541. Franco Maloberti, Yonyoung Choi
    86 dB DR Cross-Coupled Time-Interleaved xx ADC for Audio Signal Band with 322 µA Current Consumption. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2148-2151 [Conf]
  542. Giuseppe de Vita, Francesco Marraccini, Giuseppe Iannaccone
    Low-Voltage Low-Power CMOS Oscillator with Low Temperature and Process Sensitivity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2152-2155 [Conf]
  543. Yi-Bin Hsieh, Yao-Huang Kao
    A Fully Integrated Spread Spectrum Clock Generator Using Two-Point Delta-Sigma Modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2156-2159 [Conf]
  544. Hong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai
    A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2160-2163 [Conf]
  545. Alfredo Olmos, Andre Vilas Boas, Jefferson Soldera
    A Sub-1V Low Power Temperature Compensated Current Reference. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2164-2167 [Conf]
  546. Erhan Ozalevli, Walter Huang, Paul E. Hasler, David V. Anderson
    VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2168-2171 [Conf]
  547. D. DiClemente, F. Yuan
    Current-Mode Phase-Locked Loops with Low Supply Voltage Sensitivity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2172-2175 [Conf]
  548. Yuxin Wang, Zeljko Ignjatovic
    On-Chip Substrate Noise Suppression Using Clock Randomization Methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2176-2179 [Conf]
  549. Jie Qin, Charles E. Stroud, Foster F. Dai
    Noise Figure Measurement Using Mixed-Signal BIST. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2180-2183 [Conf]
  550. Tsung-Chu Huang, Gau-Bin Chang, Ling Li
    Congruence Synchronous Mirror Delay. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2184-2187 [Conf]
  551. Song Guo, Hoi Lee
    Dual Active-Capacitive-Feedback Compensation for Area-Efficient Three-Stage Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2188-2191 [Conf]
  552. K. Park, W. S. Oh, B.-Y. Choi, J.-W. Han, S. M. Park
    A 4-channel 12.5Gb/s Common-Gate Transimpedance Amplifier Array for DVI/HDMI Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2192-2195 [Conf]
  553. V. Stornelli, G. Ferri, A. De Marcellis, Christian Falconi, D. Mazzieri, Arnaldo D'Amico
    High-Accuracy, High-Precision DEM-CCII Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2196-2199 [Conf]
  554. Jose Luis Ruiz-Chavira, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, Antonio B. Torralba
    Low-Voltage CMOS Single Ended and Fully Differential Amplifier with Programmable Gain. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2200-2203 [Conf]
  555. Christian Falconi, M. Cianella, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
    Mismatch-tolerant, Continuous Time, Gain Enhanced Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2204-2207 [Conf]
  556. Hsiao Wei Su, Zhi Hua Wang
    The Impact of Different Gain Control Methods on Performance of CMOS Variable-Gain LNA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2208-2211 [Conf]
  557. Christian Falconi, Arnaldo D'Amico, Gianluca Giustolisi, Gaetano Palumbo
    Rosenstark-like Representation of Feedback Amplifier Resistance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2212-2215 [Conf]
  558. Walter Aloisi, Giuseppe Di Cataldo, Gaetano Palumbo, Salvatore Pennisi
    Miller Compensation: Optimization with Current Buffer/Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2216-2219 [Conf]
  559. Bradley A. Minch
    Low-Voltage Wilson Current Mirrors in CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2220-2223 [Conf]
  560. Michael Trakimas, Sameer R. Sonkusale
    A 0.5V Bulk-Input Operational Transconductance Amplifier with Improved Common-Mode Feedback. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2224-2227 [Conf]
  561. Jacek Piskorowski
    On Problems of Compensated Continuous-Time Chebyshev Filters in the Time Domain. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2228-2231 [Conf]
  562. Bob Schell, Yannis P. Tsividis
    Analysis of Continuous-Time Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2232-2235 [Conf]
  563. Fabian Henrici, Joachim Becker, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli
    A Continuous-Time Field Programmable Analog Array Using Parasitic Capacitance Gm-C Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2236-2239 [Conf]
  564. Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Salvatore Pennisi
    Source-degenerated CMOS Transconductor with Auxiliary Linearization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2240-2243 [Conf]
  565. Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
    Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2244-2247 [Conf]
  566. Shunsuke Koshita, Yousuke Mizukami, Taketo Konno, Masahide Abe, Masayuki Kawamata
    Analysis of Second-Order Modes of Linear Continuous-Time Systems under Positive-Real Transformations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2248-2251 [Conf]
  567. Gholamreza Nikandish, Behnam Sedighi, Mehrdad Sharif Bakhtiar
    Performance Comparison of Switched-Capacitor and Switched-Current Pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2252-2255 [Conf]
  568. Maria Drakaki, Alkis A. Hatzopoulos, Stylianos Siskos
    CMOS Inductor Performance Estimation using Z- and S-parameters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2256-2259 [Conf]
  569. Emad Hegazi
    An Algorithm for Automatic Tuning of PLLs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2260-2263 [Conf]
  570. Alexander Buhmann, Matthias Keller, Maurits Ortmanns, Yiannos Manoli
    Estimating Circuit Nonidealities of Continuous-Time Multibit Delta-Sigma Modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2264-2267 [Conf]
  571. Aly E. Salama, Sherif M. Sharroush, Mahmoud Y. Fekry
    Increasing the Sense Margin of 1T-1C Ferroelectric Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2268-2271 [Conf]
  572. Dayong Li, Ming Liu, Wei Wang
    Fault Tolerance Circuit for AM-OLED. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2272-2274 [Conf]
  573. Nicole M. Nelson, Pamela Abshire
    Chopper Modulation Improves OTA Information Transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2275-2278 [Conf]
  574. David Wolpert, Paul Ampadu
    Temperature-Robust Performance Yield through Supply Voltage Selection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2279-2282 [Conf]
  575. Amir Hosseini, Yehia Massoud
    Subwavelength Plasmonic Bragg Reflector Structures for On-chip Optoelectronic Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2283-2286 [Conf]
  576. Takayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga
    Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2287-2290 [Conf]
  577. Wei Xing Zheng
    An Efficient Method for Estimation of Autoregressive Signals Subject to Colored Noise. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2291-2294 [Conf]
  578. Mahdi Shabany, P. Glenn Gulak
    Application of Sequential Monte Carlo to M-QAM Schemes in the Presence of Nonlinear Solid-State Power Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2295-2298 [Conf]
  579. Ut-Va Koc
    PLL-Free Quadrature-Amplitude Modulation in Coherent Optical Communication. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2299-2302 [Conf]
  580. Hon Keung Kwan, Aimin Jiang
    Peak-Contrained WLS Strategy for FIR Digital Filter Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2303-2306 [Conf]
  581. C. C. Tseng
    Eigenvector and Fractionalization of Discrete Hadamard Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2307-2310 [Conf]
  582. Naoto Sasaoka, Masatoshi Watanabe, Yoshio Itoh, Kensaku Fujii
    Noise Reduction System Based on LPEF and System Identification with Variable Step Size. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2311-2314 [Conf]
  583. Mohammed A. Hasan
    Lagrangian Gradient for Principal Singular Component Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2315-2318 [Conf]
  584. Alessandro Bastari, Stefano Squartini, Francesco Piazza
    Discrete Stockwell Transform and Reduced Redundancy Versions from Frame Theory Viewpoint. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2319-2322 [Conf]
  585. Robin Moritz, Henry Leung, Xinping Huang
    Nonlinear Compensation for High Power Amplifiers using Genetic Programming. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2323-2326 [Conf]
  586. K. G. Smitha, A. Prasad Vinod
    A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2327-2330 [Conf]
  587. Sai Mohan Kilambi, Behrouz Nowrouzian
    A Diversity Controlled Genetic Algorithm for Optimization of FRM Digital Filters over DBNS Multiplier Coefficient Space. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2331-2334 [Conf]
  588. Oscar Gustafsson, Håkan Johansson
    Complexity Comparison of Linear-Phase Mth-Band and General FIR Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2335-2338 [Conf]
  589. Aimin Jiang, Hon Keung Kwan
    IIR Digital Filter Design with Novel Stability Criterion Based on Argument Principle. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2339-2342 [Conf]
  590. Ngai Wong, Chi-Un Lei
    FIR Filter Approximation by IIR Filters Based on Discrete-Time Vector Fitting. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2343-2346 [Conf]
  591. Md. Imamul Hassan Bhuiyan, M. Omair Ahmad, M. N. S. Swamy
    New Spatially Adaptive Wavelet-based Method for the Despeckling of Medical Ultrasound Images. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2347-2350 [Conf]
  592. Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud
    A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2351-2354 [Conf]
  593. Xin-Kai Chen, GuoLin Li, Xiang Xie, Xiaowen Li, Zhihua Wang, Hong Chen
    A Low Power Digital Baseband for Wireless Endoscope Capsule. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2355-2358 [Conf]
  594. Yan Huang, Emmanuel M. Drakakis, Chris Toumazou
    A Wide Tuning Range CMOS Oscillator for an Optoelectronic Retinal Prosthesis System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2359-2362 [Conf]
  595. T. Hui Teo, Gin Kooi Lim, Darwin Sutomo David, Kuo Hwi Tan, Pradeep Kumar Gopalakrishnan, Rajnder Singh
    Ultra Low-Power Sensor Node for Wireless Health Monitoring System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2363-2366 [Conf]
  596. Xiao Liu, Andreas Demosthenous, Nick Donaldson
    A Safe Transmission Strategy for Power and Data Recovery in Biomedical Implanted Devices. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2367-2370 [Conf]
  597. Awais M. Kamboh, Matthew Raetz, Andrew Mason, Karim G. Oweiss
    Area-Power Efficient Lifting-Based DWT Hardware for Implantable Neuroprosthetics. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2371-2374 [Conf]
  598. Dylan Banks, Patrick Degenaar, Chris Toumazou
    A Bio-Inspired Adaptive Retinal Processing Neuron with Multiplexed Spiking Outputs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2375-2378 [Conf]
  599. Paulo Alexandre Crisóstomo Lopes, J. Germano, T. M. Almeida, Leonel Sousa, Moisés Simões Piedade, Filipe Cardoso, H. A. Ferreira, P. P. Freitas
    A New Handheld Biochip-based Microsystem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2379-2382 [Conf]
  600. Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Yan-Jhin Ciou, I-Yu Huang, Chih-Peng Li, Yun-Chin Lee, Wen-Jen Wu
    An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2383-2386 [Conf]
  601. Tara Julia Hamilton, Craig T. Jin, André van Schaik
    A Basilar Membrane Resonator for an Active 2-D Cochlea. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2387-2390 [Conf]
  602. Roy H. Olsson, Bianca E. N. Keeler, David A. Czaplewski, Dustin W. Carr
    Circuit Techniques for Reducing Low Frequency Noise in Optical MEMS Position and Inertial Sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2391-2394 [Conf]
  603. Edwin J. Tan, Zeljko Ignjatovic, Mark F. Bocko
    A CMOS Image Sensor with Focal Plane Discrete Cosine Transform Computation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2395-2398 [Conf]
  604. M. K. Law, Amine Bermak
    A CMOS Image Sensor using Variable Reference Time Domain Encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2399-2402 [Conf]
  605. H. H. Chen, S. C. Chan, K. L. Ho
    New Recursive Adaptive Beamforming Algorithms for Uniform Concentric Spherical Arrays with Frequency Invariant Characteristics. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2403-2406 [Conf]
  606. Shi-Bing Wang, Yufei Zhou, Herbert H. C. Iu, Jun-Ning Chen
    Complex Phenomena in SEPIC Converter Based on Sliding Mode Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2407-2410 [Conf]
  607. Anna Richelli, Luca Mensi, Luigi Colalongo, Zsolt Kovacs, Pier Luigi Rolandi
    A 1.2V-5V High Efficiency CMOS Charge Pump for Non-Volatile Memories. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2411-2414 [Conf]
  608. C. Peters, O. Kessling, Fabian Henrici, Maurits Ortmanns, Yiannos Manoli
    CMOS Integrated Highly Efficient Full Wave Rectifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2415-2418 [Conf]
  609. Yuehui Huang, Herbert H. C. Iu, Chi K. Michael Tse
    Boundaries Between Fast-and Slow-Scale Bifurcations in Parallel-Connected Buck Converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2419-2422 [Conf]
  610. E. Rodriguez, Gerard Villar, Francesc Guinjoan, Alberto Poveda, A. El-Aroudi, Eduard Alarcón
    General-purpose ripple-based fast-scale instability prediction in switching power regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2423-2426 [Conf]
  611. Hanwu Sun, Louis Shue
    Analysis of an Adaptive Filter-bank for Harmonic Measurement and Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2427-2430 [Conf]
  612. T. Sulawa, Zivan Zabar, Dariusz Czarkowski, L. Birenbaum, S. Lee, Y. TenAmi
    Short Circuit Current of Induction Generators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2431-2434 [Conf]
  613. Chua-Chin Wang, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng
    A Low-power Sensorless Inverter Controller of Brushless DC Motors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2435-2438 [Conf]
  614. Wanping Zhang, Chung-Kuan Cheng
    Incremental Power Impedance Optimization Using Vector Fitting Modeling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2439-2442 [Conf]
  615. Leontina Pinto, Rodrigo Maia, Leandro Tsunechiro, Jacques Szczupak, Bruno Dias
    Risk Management - beyond Risk Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2443-2446 [Conf]
  616. Li Zhang, Baoyong Chi, Zhihua Wang, Hongyi Chen, Jinke Yao, Ende Wu
    A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2447-2450 [Conf]
  617. R. Berner, Tobi Delbrück, Antón Civit-Balcells, Alejandro Linares-Barranco
    A 5 Meps $100 USB2.0 Address-Event Monitor-Sequencer Interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2451-2454 [Conf]
  618. Tolga Kaya, Hur Koser, Eugenio Culurciello
    A Silicon-on-Sapphire Low-Voltage Temperature Sensor for Energy Scavengers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2455-2458 [Conf]
  619. M. di Bernardo, U. Montanaro, S. Santini
    On a novel Hybrid LQ-MCS control strategy and its application to a DC motor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2459-2462 [Conf]
  620. Jaber A. Abu-Qahouq, Lilly Huang
    A Converter with Fixed Switching Frequency Adaptive Multi-Mode Control Scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2463-2465 [Conf]
  621. Hongbin Chen, Jiuchao Feng, Chi K. Michael Tse
    A General Noncoherent Chaos-Shift-Keying Communication System and its Performance Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2466-2469 [Conf]
  622. Chunyan Wang
    A Method to Reduce the Effect of the Switching Noise in Analog-Mixed Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2470-2473 [Conf]
  623. Tetsushi Ueta, Takuji Kousaka, Shigeki Tsuji
    Occasional Delayed Feedback Control for Switched Autonomous Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2474-2477 [Conf]
  624. Zhibo Zhou, Tong Zhou, Jinxiang Wang
    Performance of Multi-User DCSK Communication System Over Multipath Fading Channels. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2478-2481 [Conf]
  625. Salih Ergün, Serdar Özoguz
    A Chaos-Modulated Dual Oscillator-Based Truly Random Number Generator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2482-2485 [Conf]
  626. Kuniyasu Shimizu, Hisa-Aki Tanaka, Osamu Masugata, Tetsuro Endo
    Phase Synchronization in Injection-'Un'locking Oscillator Arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2486-2489 [Conf]
  627. Régis Roubadia, Sami Ajram, Guy Cathébras
    Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2490-2493 [Conf]
  628. Jin Zhou, Junan Lu, Jinhu Lu
    Adaptive Pinning Synchronization of A General Complex Dynamical Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2494-2497 [Conf]
  629. Eugenio Culurciello, Pujitha Weerakoon
    Vertically-Integrated Three-Dimensional SOI Photodetectors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2498-2501 [Conf]
  630. Bo Wang, Zhihai He
    Distributed Optimization Over Wireless Sensor Networks using Swarm Intelligence. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2502-2505 [Conf]
  631. Chung-Ching Shen, Roni Kupershtok, Bo Yang, Felice Maria Vanin, Xi Shao, Datta Sheth, Neil Goldsman, Quirino Balzano, Shuvra S. Bhattacharyya
    Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2506-2509 [Conf]
  632. Fariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed
    A New 10 Gbps Traffic Management algorithm for High-speed Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2510-2513 [Conf]

  633. A New 10 Gbps Traffic Management algorithm for High-speed Networks. [Citation Graph (, )][DBLP]

  634. R. Mahesh, A. Prasad Vinod
    An Architecture For Integrating Low Complexity and Reconfigurability for Channel filters in Software Defined Radio Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2514-2517 [Conf]
  635. R. Mahesh, A. Prasad Vinod
    Frequency Response Masking based Reconfigurable Channel Filters for Software Radio Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2518-2521 [Conf]
  636. Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta
    On the Suitability of Discrete-Time Receivers for Software-Defined Radio. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2522-2525 [Conf]
  637. Faheem Sheikh, Shahid Masud
    Improved Factorization for Sample Rate Conversion In Software Defined Radios. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2526-2529 [Conf]
  638. Nathan M. Neihart, Sumit Roy, David J. Allstot
    A Parallel, Multi-Resolution Sensing Technique for Multiple Antenna Cognitive Radios. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2530-2533 [Conf]
  639. Brad R. Jackson, You Zheng, Carlos E. Saavedra
    A CMOS Direct-Digital BPSK Modulator Using an Active Balun and Common-Gate Switches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2534-2537 [Conf]
  640. Chueh-Hao Yu, Day-Uei Li
    A 2.5 Gb/s CMOS Burst-Mode Limiting Amplifier for GPON System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2538-2541 [Conf]
  641. Ivan Chee Hong Lai, Yuki Kambayashi, Minoru Fujishima
    50GHz Double-Balanced Up-Conversion Mixer Using CMOS 90nm Process. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2542-2545 [Conf]
  642. Day-Uei Li, Wen-Hui Chen, Long-Xi Chang, Chueh-Hao Yu
    A 3.8-Gb/s CMOS Laser Driver with Automatic Power Control Using Thermistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2546-2549 [Conf]
  643. A. Tang, F. Yuan, E. Law
    A New CMOS BPSK Modulator with Optimal Transaction Bandwidth Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2550-2553 [Conf]
  644. Nader Kalantari, Michael M. Green
    All-CMOS High-Speed CML Gates with Active Shunt-Peaking. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2554-2557 [Conf]
  645. Ji-Yong Jeong, Gil-Su Kim, Seung-Hoon Oh, Kyu-young Kim, Soo-Won Kim
    The Wide Input Range Automatic-Threshold Control Circuit for High Definition Digital Audio Interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2558-2561 [Conf]
  646. Yike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang, Yongming Li, Zhihua Wang, Patrick Chiang
    Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2562-2565 [Conf]
  647. Ahmed Saad, Khaled M. Sharaf
    A Fully Integrated 2.4GHz CMOS Frequency Synthesizer Using a Ring-Based VCO with Inductive Peaking. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2566-2569 [Conf]
  648. W. Kenneth Jenkins, C. Radhakrishnan, S. Pal
    Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2570-2573 [Conf]
  649. Zhuo Xu, Junyan Ren, Xue-Jing Wang, Fan Ye
    Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2574-2577 [Conf]
  650. Jing Wang, Lang Mai, Yanjie Peng, Jun Han, Xiaoyang Zeng
    An Energy-Proportion Synchronization Method for IR-UWB Communications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2578-2581 [Conf]
  651. Zhen-qing Guo, Yang Xiao, Moon Ho Lee
    Multiuser Detection Based on Particle Swarm Optimation Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2582-2585 [Conf]
  652. Afshin Niktash, Hooman Parizi, Nader Bagherzadeh
    Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2586-2589 [Conf]
  653. Seungbeom Lee, Sin-Chong Park
    Modified SDF Architecture for Mixed DIF/DIT FFT. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2590-2593 [Conf]
  654. Liang Liu, Junyan Ren, Xuejing Wang, Fan Ye
    Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2594-2597 [Conf]
  655. Chitranjan K. Singh, Naofal Al-Dhahir, Poras T. Balsara
    Effect of Word-length Precision on the Performance of MIMO Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2598-2601 [Conf]
  656. Chun-Hao Liao, To-Ping Wang, Tzi-Dar Chiueh
    A Novel Low-Complexity Rayleigh Fader for Real-Time Channel Modeling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2602-2605 [Conf]
  657. To-Ping Wang, Chun-Hao Liao, Tzi-Dar Chiueh
    A Real-Time Digital Baseband MIMO Channel Emulation System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2606-2609 [Conf]
  658. Johan Eilert, Di Wu, Dake Liu
    Efficient Complex Matrix Inversion for MIMO Software Defined Radio. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2610-2613 [Conf]
  659. K. K. O, C. Cao, E.-Y. Seok, S. Sankaran
    CMOS Millimeter-Wave Signal Sources and Detectors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2614-2617 [Conf]
  660. Ro-Min Weng, Po-Cheng Lin
    A 1.5-V Low-Power Common-Gate Low Noise Amplifier for Ultrawideband Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2618-2621 [Conf]
  661. Hamid Nejati, Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud
    Modeling and Design of Ultrawideband Low Noise Amplifiers with Generalized Impedance Matching Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2622-2625 [Conf]
  662. F. Plessas, A. Papalambrou, G. Kalivas
    A Subharmonic Injection-Locked Self-Oscillating Mixer. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2626-2629 [Conf]
  663. J. L. Lopez, Jordi Teva, Arantxa Uranga, F. Torres, Jaume Verd, Gabriel Abadal, Nuria Barniol, Jaume Esteve, Francesc Pérez-Murano
    Mixing in a 220MHz CMOS-MEMS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2630-2633 [Conf]
  664. Jinhu Lu, Derong Liu
    A Brief Overview of the Complex Biological and Engineering Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2634-2637 [Conf]
  665. Chai Wah Wu
    On two approaches to analyzing consensus in complex networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2638-2641 [Conf]
  666. Jin Fan, Xiao Fan Wang, Xiang Li
    Enhancing Synchronizabilities of Power-Law Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2642-2645 [Conf]
  667. Wallace K. S. Tang, Mao Yu, Ljupco Kocarev
    Identification and monitoring of biological neural network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2646-2649 [Conf]
  668. Liang Chen, Jinhu Lu, Junan Lu
    Synchronization of the Time-Varying Discrete Biological Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2650-2653 [Conf]
  669. Susu Yao, Weisi Lin, Ee Ping Ong, Zhongkang Lu, Mei Hwan Loke, Zhengguo Li
    Image Quality Assessment using Foveated Wavelet Error Sensitivity and Isotropic Contrast. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2654-2657 [Conf]
  670. Ruth Aguilar-Ponce, J. Luis Tecpanecatl-Xihuitl, Ashok Kumar, Magdy Bayoumi
    Pixel-Level Image Fusion Scheme based on Linear Algebra. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2658-2661 [Conf]
  671. Gwo Giun Lee, Hsin-Te Li, Ming-Jiun Wang, He-Yuan Lin
    Motion Adaptive Deinterlacing via Edge Pattern Recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2662-2665 [Conf]
  672. Kaushik Gopalan, Takis Kasparis
    Background stabilization and debris flagging in launch pad videos. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2666-2669 [Conf]
  673. Yu-chia Chung, Zhihai He
    Low-Complexity and Reliable Moving Objects Detection and Tracking for Aerial Video Surveillance with Small UAVS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2670-2673 [Conf]
  674. David López Vilariño, Victor M. Brea, Vicente Moreno, Diego Cabello
    CNN Implementation of Spin Filters for Electronic Speckle Pattern Interferometry Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2674-2677 [Conf]
  675. David Lopez Vilarino, Piotr Dudek
    Evolution of Pixel Level Snakes towards an efficient hardware implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2678-2681 [Conf]
  676. Natalia A. Fernandez-Garcia, Victor M. Brea, Diego Cabello
    Area and Time Efficient Cellular Non-linear Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2682-2685 [Conf]
  677. Dietmar Fey, Marcus Komann, Frank Schurz, Andreas Loos
    An Organic Computing architecture for visual microprocessors based on Marching Pixels. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2686-2689 [Conf]
  678. Carlos M. Domínguez-Matas, Ricardo Carmona-Galán, F. J. Sanchez-Fernandez, A. Rodriguez-Vazquez
    A Focal-Plane Image Processor for Low Power Adaptive Capture and Analysis of the Visual Stimulus. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2690-2693 [Conf]
  679. João M. S. Silva, L. Miguel Silveira
    On the Effectiveness of Reducing Large Linear Networks with Many Ports. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2694-2697 [Conf]
  680. Janakiram G. Sankaranarayanan, Kartikeya Mayaram
    Noise Simulation and Modeling for MEMS Varactor Based RF VCOs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2698-2701 [Conf]
  681. Angan Das, Ranga Vemuri
    GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2702-2705 [Conf]
  682. He Peng, Chung-Kuan Cheng
    Fast Transient Simulation of Lossy Transmission Lines. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2706-2709 [Conf]
  683. Fan Yang, Xuan Zeng, Yangfeng Su, Dian Zhou
    RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2710-2713 [Conf]
  684. Hon Keung Kwan, Aimin Jiang
    Design of IIR Variable Fractional Delay Digital Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2714-2717 [Conf]
  685. Takao Hinamoto, Toru Oumi, Osemekhian I. Omoifo, Wu-Sheng Lu
    On Frequency-Weighted l2-Sensitivity Analysis and Minimization of 2-D State-Space Digital Filters Subject to l2-Scaling Constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2718-2721 [Conf]
  686. Shunsuke Yamaki, Masahide Abe, Masayuki Kawamata
    A Fast Convergence Algorithm for L2-Sensitivity Minimization of 2-D Separable-Denominator State-Space Digital Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2722-2725 [Conf]
  687. C. C. Tseng
    Digital Integrator Design Using Recursive Romberg Integration Rule and Fractional Sample Delay. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2726-2729 [Conf]
  688. Seung-Jin Lee, Sunyoung Kim, Hoi-Jun Yoo
    A Low Power Digital Signal Processor with Adaptive Band Activation for Digital Hearing Aid Chip. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2730-2733 [Conf]
  689. Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
    Dynamic Reconfigurability in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2734-2737 [Conf]
  690. Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi
    System-Level Design for Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2738-2741 [Conf]
  691. Chun-Hsian Huang, Kai-Jung Shih, Chao-Sheng Lin, Shih-Shiue Chang, Pao-Ann Hsiung
    Dynamically Swappable Hardware Design in Partially Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2742-2745 [Conf]
  692. Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich
    Modeling and Synthesis of Hardware-Software Morphing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2746-2749 [Conf]
  693. Yana Yankova, Koen Bertels, Stamatis Vassiliadis, Roel Meeuws, Arcilio Virginia
    Automated HDL Generation: Comparative Evaluation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2750-2753 [Conf]
  694. Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yar-Sun Hsu
    A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2754-2757 [Conf]
  695. Daesun Oh, Keshab K. Parhi
    Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2758-2761 [Conf]
  696. Francois Nougarou, Daniel Massicotte, Messaoud Ahmed-Ouameur
    Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems: Part II - FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2762-2765 [Conf]
  697. Ashkan Ashrafi, Aleksandar Milenkovic, Reza Adhami
    A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2766-2769 [Conf]
  698. Matthias May, Christian Neeb, Norbert Wehn
    Evaluation of High Throughput Turbo-Decoder Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2770-2773 [Conf]
  699. Zhiyu Liu, Volkan Kursun
    High Read Stability and Low Leakage Cache Memory Cell. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2774-2777 [Conf]
  700. Olivier Thomas, Marina Reyboz, Marc Belleville
    Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2778-2781 [Conf]
  701. Chun-Chen Yeh, Eugenio Culurciello
    Nonvolatile Flash Memories in Silicon-on-sapphire CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2782-2785 [Conf]
  702. Daniel R. Blum, José G. Delgado-Frias
    Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2786-2789 [Conf]
  703. Afshin Nourivand, Chunyan Wang, M. Omair Ahmad
    An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2790-2793 [Conf]
  704. Haolu Xie, Xin Wang, Albert Z. Wang, Bo Qin, Hongyi Chen, Yumei Zhou, Bin Zhao
    A Varying Pulse Width Second Order Derivative Gaussian Pulse Generator for UWB Transceivers in CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2794-2797 [Conf]
  705. Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma
    An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2798-2801 [Conf]
  706. Chyuen-Wei Ang, Yuanjin Zheng, Chun-Huat Heng
    A Multi-band CMOS Low Noise Amplifier for Multi-standard Wireless Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2802-2805 [Conf]
  707. Jingyu Hu, Mike R. May, Matt D. Felder, Len DiSanza, Lawrence H. Ragan
    A Fully Integrated Inductorless Low Noise Amplifier with 1dB-Step Programmable Gain for FM Radio Receiver Front-End. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2806-2809 [Conf]
  708. Mark Tuckwell, Christos Papavassiliou
    Exploration of energy requirements at the output of an LNA from a thermodynamic perspective. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2810-2813 [Conf]
  709. Shunsuke Koshita, Masahide Abe, Masayuki Kawamata
    State-Space Analysis of Power Complementary Analog Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2814-2817 [Conf]
  710. Mustafa Acar, Anne-Johan Annema, Bram Nauta
    Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2818-2821 [Conf]
  711. Shyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch
    Optimal Synthesis of MITE Translinear Loops. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2822-2825 [Conf]
  712. B. Robert Gregoire, Un-Ku Moon
    Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite Resistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2826-2829 [Conf]
  713. Haibo Fei, Randall L. Geiger
    Linear Current Division Principles. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2830-2833 [Conf]
  714. Alexander Fish, Tomer Rothschild, Avichay Hodes, Yonatan Shoshan, Orly Yadid-Pecht
    Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) Approach. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2834-2837 [Conf]
  715. Zhiqiang Lin, Michael W. Hoffman, Walter D. Leon, Nathan Schemm, Sina Balkir
    A CMOS Front-End for a Lossy Image Compression Sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2838-2841 [Conf]
  716. Zheng Yang, Viktor Gruev, Jan Van der Spiegel
    Low Fixed Pattern Noise Current-mode Imager Using Velocity Saturated Readout Transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2842-2845 [Conf]
  717. Viktor Gruev, Zheng Yang, Jan Van der Spiegel, Ralph Etienne-Cummings
    Two Transistor Current Mode Active Pixel Sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2846-2849 [Conf]
  718. Francisco Serra-Graells, J. M. Margarit, Lluís Terés
    A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2850-2853 [Conf]
  719. Xiang Gao, Eric A. M. Klumperink, Bram Nauta
    Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2854-2857 [Conf]
  720. Essam Atalla, Emad Hegazi, M. Marzouk Ibrahim
    On the Design of Error Cancellation Network for MASH Sigma-Delta-Frequency discriminators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2858-2861 [Conf]
  721. Raghuram Jonnalagedda, Kartikeya Mayaram
    Design of Very Low Noise 4.2GHz Clapp VCOs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2862-2865 [Conf]
  722. Chung-Yu Wu, Shun-Wei Hsu, Wen-Chieh Wang
    A 24-GHz CMOS Current-Mode Power Amplifier with High PAE and Output Power. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2866-2869 [Conf]
  723. Chao Yang, Andrew Mason
    Precise RSSI with High Process Variation Tolerance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2870-2873 [Conf]
  724. Andreas G. Andreou, Jie Chen, Pau-Choo Chung, Stephen T. C. Wong
    Enabling Technologies in Drug Delivery and Clinical Care. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2874-2877 [Conf]
  725. Xiaobo Zhou, Jian Chen, Jinmin Zhu, Fuhai Li, Xudong Huang, Stephen T. C. Wong
    Study of CuO Nanoparticle-induced Cell Death by High Content Cellular Fluorescence Imaging and Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2878-2881 [Conf]
  726. James Xing, Jie Zeng, Jing Yang, Tao Kong, Tao Xu, Wilson Roa, Xiaoping Wang, Jie Chen
    Gold-Based Nanoparticles for Breast Cancer Diagnosis and Treatment. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2882-2885 [Conf]
  727. Jennifer Blain Christen, Andreas G. Andreou, Brian Iglehart
    Localized closed-loop temperature control and regulation in hybrid silicon/silicone life science microsystems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2886-2889 [Conf]
  728. Ching-Hsing Luo, Po-Yuan Chen, Chun-Hao Teng, Sheng-Nan Wu, Ruey-Jen Sung
    Reliability Analysis of Physiological Phenomena by Cardiac Action Potential Model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2890-2893 [Conf]
  729. Stephen Warrington, Subramania Sudharsanan, Wai-Yip Chan
    Architecture for Multiple Reference Frame Variable Block Size Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2894-2897 [Conf]
  730. Hyojin Choi, Wonchul Lee, Wonyong Sung
    Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2898-2901 [Conf]
  731. Der-Chun Cherng, Shao-Yi Chien
    Video Segmentation with Model-Based Sprite Generation for Panning Surveillance Cameras. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2902-2905 [Conf]
  732. Yu Li, Yanmei Qu, Yun He
    Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2906-2909 [Conf]
  733. Dajiang Zhou, Peilin Liu
    A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2910-2913 [Conf]
  734. Paolo Arena, G. Buscemi, B. Carambia, C. Del Negro, Luigi Fortuna, Mattia Frasca, A. Vicari
    Models of Lava Flow Through the CNN-Based E^3 Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2914-2917 [Conf]
  735. Christian Merkwirth, Maciej Ogorzalek
    Applying CNN to Cheminformatics. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2918-2921 [Conf]
  736. Matthias Güdemann, Andreas Angerer, Frank Ortmeier, Wolfgang Reif
    Modeling of self-adaptive systems with SCADE. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2922-2925 [Conf]
  737. Eric K. C. Tsang, Bertram Emil Shi
    Probabilistic Modelling of Phase-tuned Disparity Energy Neuron Populations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2926-2929 [Conf]
  738. Gunter Geis, Frank Gollas, Ronald Tetzlaff
    On the Implementation of Cellular Wave Computing Methods by Hardware Learning. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2930-2933 [Conf]
  739. Henry H. Y. Chan, Zeljko Zilic
    A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2934-2937 [Conf]
  740. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Scalable Gate-Level Models for Power and Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2938-2941 [Conf]
  741. Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara
    Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2942-2945 [Conf]
  742. Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
    A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2946-2949 [Conf]
  743. Alonso Morgado, Rocio del Río, José Manuel de la Rosa
    A SIMULINK Block Set for the High-Level Simulation of Multistandard Radio Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2950-2953 [Conf]
  744. Zhiping Lin, Yongzhi Liu
    FRM Filter Design with Group Delay Constraint Using Second-Order Cone Programming. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2954-2957 [Conf]
  745. Yong Lian, Chun Zhu Yang, Yong Ching Lim
    Complexity Reduction of FRM Filters via Multiplication-Free Prefilter-Equalizer Structures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2958-2961 [Conf]
  746. Y. C. Lim, Y. J. Yu, K. L. Teo, Tapio Saramäki
    FRM-Based FIR Filters with Minimum Coefficient Sensitivities. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2962-2965 [Conf]
  747. T. Q. Hung, H. D. Tuan, T. Q. Nguyen
    Design of Diamond and Circular Filters by Semi-definite Programming. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2966-2969 [Conf]
  748. Xiaoping Lai, Hon Keung Kwan
    An Online Procedure for Linear-Phase 2-D FIR Filters of Smallest Size with Magnitude Error Constraint. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2970-2973 [Conf]
  749. Anthony Lombard, Herbert Buchner, Walter Kellermann
    Improved Wideband Blind Adaptive System Identification Using Decorrelation Filters for the Localization of Multiple Speakers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2974-2977 [Conf]
  750. Malay Gupta, Scott C. Douglas
    Performance Evaluation of Convolutive Blind Source Separation of Mixtures of Unequal-Level Speech Signals. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2978-2981 [Conf]
  751. Intae Lee, Te-Won Lee
    On Modelling the Frequency Components of Speech with Norm-Invariant Joint Densities. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2982-2985 [Conf]
  752. Tomohiro Nakatani, Takafumi Hikichi, Keisuke Kinoshita, Takuya Yoshioka, Marc Delcroix, Masato Miyoshi, Biing-Hwang Juang
    Robust blind dereverberation of speech signals based on characteristics of short-time speech segments. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2986-2989 [Conf]
  753. Biing-Hwang Juang, Tomohiro Nakatani
    Joint Source-Channel Modeling and Estimation for Speech Dereverberation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2990-2993 [Conf]
  754. Arash Ahmadi, Mark Zwolinski
    Multiple-Width Bus Partitioning Approach to Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2994-2997 [Conf]
  755. Massimo Alioto, Gaetano Palumbo
    High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2998-3001 [Conf]
  756. R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan
    On the Hardware Reduction of z-Datapath of Vectoring CORDIC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3002-3005 [Conf]
  757. Amir Agah, Seid Mehdi Fakhraie, Azita Emami-Neyestanak
    Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3006-3009 [Conf]
  758. Xuehai Qian, Hao Zhang, Jingang Yang, He Huang, Junchao Zhang, Dongrui Fan
    Circuit implementation of floating point range reduction for trigonometric functions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3010-3013 [Conf]
  759. Byung-Do Yang, Jae-Eun Lee, Jang-Su Kim, Junghyun Cho, Seung-Yun Lee, Byoung-Gon Yu
    A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3014-3017 [Conf]
  760. Jungseob Lee, Azadeh Davoodi
    Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3018-3021 [Conf]
  761. Bastien Giraud, Amara Amara, Andrei Vladimirescu
    A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3022-3025 [Conf]
  762. Sang-uhn Cha, Hongil Yoon
    High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3026-3029 [Conf]
  763. Sandeep Patil, Michael Wieckowski, Martin Margala
    A Self-Biased Charge-Transfer Sense Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3030-3033 [Conf]
  764. Tamer A. Abdelrahim, Tarek Elesseily, Ahmed Saad Abdou, Khaled M. W. Sharaf
    A 12-mW Fully Integrated Low-IF dual-band GPS Receiver on 0.13-µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3034-3038 [Conf]
  765. Kenneth A. Townsend, James W. Haslett, John Nielsen
    A CMOS Integrated Power Detector for UWB. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3039-3042 [Conf]
  766. Tuan-Anh Phan, Vladimir Krizhanovskii, Seok-Kyun Han, Sang-Gug Lee, Hyun-Seo Oh, Nae-Soo Kim
    4.7pJ/pulse 7th Derivative Gaussian Pulse Generator for Impulse Radio UWB. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3043-3046 [Conf]
  767. Muhammad Usama, Tad A. Kwasniewski
    A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3047-3050 [Conf]
  768. Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang
    A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3051-3054 [Conf]
  769. Arindam Basu, Ryan W. Robucci, Paul E. Hasler
    A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating over Seven Decades of Current. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3055-3058 [Conf]
  770. Adnan Gundel, William N. Carr
    Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3059-3062 [Conf]
  771. Johan Raman, Pieter Rombouts, Ludo Weyten
    An Unconstrained Architecture for High-Order Sigma Delta Force-Feedback Inertial Sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3063-3066 [Conf]
  772. Matti Paavola, Mikko Saukoski, Mika Laiho, Kari Halonen
    A Micropower Voltage, Current, and Temperature Reference for a Low-Power Capacitive Sensor Interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3067-3070 [Conf]
  773. Balaji Jayaraman, Navakanta Bhat
    High Precision 16-bit Readout Gas Sensor Interface in 0.13µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3071-3074 [Conf]
  774. Jesús Costas-Santos, Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, Bernabé Linares-Barranco
    An AER Contrast Retina with On-Chip Calibration. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3075-3078 [Conf]
  775. Rico Moeckel, Shih-Chii Liu
    Motion Detection Circuits for a Time-To-Travel Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3079-3082 [Conf]
  776. Matthias Oster, Patrick Lichtsteiner, Tobi Delbrück, Shih-Chii Liu
    A Spike-Based Saccadic Recognition System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3083-3086 [Conf]
  777. Chung-Yu Wu, Chien-Ta Huang
    A CMOS Expansion/Contraction Motion Sensor with a Retinal Processing Circuit for Z-motion Detection Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3087-3090 [Conf]
  778. D. B. Fasnacht, Tobi Delbrück
    Dichromatic spectral measurement circuit in vanilla CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3091-3094 [Conf]
  779. Jeffrey Johnson, Vipul Jain, Payam Heydari
    A Nonlinear Model for Phase Noise and Jitter in LC Oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3095-3098 [Conf]
  780. James Ayers, Kartikeya Mayaram, Terri S. Fiez
    A Low Power BFSK Super-Regenerative Transceiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3099-3102 [Conf]
  781. Holly Pekau, James W. Haslett
    A 0.18µm CMOS 2.1GHz Sub-sampling Receiver Front End with Fully Integrated Second- and Fourth-Order Q-Enhanced Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3103-3106 [Conf]
  782. Paul-Peter Sotiriadis
    Diophantine Frequency Synthesis The Mathematical Principles. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3107-3110 [Conf]
  783. Adnan Gundel, William N. Carr
    A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3111-3114 [Conf]
  784. J. N. Y. Aziz, Rafal Karakiewicz, Roman Genov, A. W. L. Chiu, B. L. Bardakjian, M. Derchansky, P. L. Carlen
    In Vitro Epileptic Seizure Prediction Microsystem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3115-3118 [Conf]
  785. Darrin J. Young, Mark A. Zurcher, Wen H. Ko, Maroun Semaan, Cliff A. Megerian
    Implantable MEMS Accelerometer Microphone for Cochlear Prosthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3119-3122 [Conf]
  786. Timothy K. Horiuchi, Dorielle Tucker, Kevin Boyle, Pamela Abshire
    Spike discrimination using amplitude measurements with a low-power CMOS neural amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3123-3126 [Conf]
  787. Ming Yin, Maysam Ghovanloo
    Using Pulse Width Modulation for Wireless Transmission of Neural Signals in a Multichannel Neural Recording System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3127-3130 [Conf]
  788. Masoud Roham, Pedram Mohseni
    A Wireless IC for Wide-Range Neurochemical Monitoring Using Amperometry and Fast-Scan Cyclic Voltammetry. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3131-3134 [Conf]
  789. Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu
    Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3135-3138 [Conf]
  790. Kuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo
    A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3139-3142 [Conf]
  791. Jian Lou, Ashish Jagmohan, Dake He, Ligang Lu, Ming-Ting Sun
    Statistical Analysis Based H.264 High Profile Deblocking Speedup. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3143-3146 [Conf]
  792. Li Zhang, Xiaolin Wu, Ning Zhang, Wen Gao, Qiang Wang, Debin Zhao
    Context-based Arithmetic Coding Reexamined for DCT Video Compression. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3147-3150 [Conf]
  793. Ke Zhang, Xiao-Yang Wu, Lu Yu
    An Area-efficient VLSI Implementation of CA-2D-VLC Decoder for AVS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3151-3154 [Conf]
  794. Mauro Di Marco, Mauro Forti, Massimo Grazzini, Paolo Nistri, Luca Pancioni
    A Study on Convergence of Competitive CNNs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3155-3158 [Conf]
  795. Norikazu Takahashi, Ken Ishitobi, Tetsuo Nishi
    Sufficient Conditions for 1-D CNNs with Opposite-Sign Templates to Perform Connected Component Detection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3159-3162 [Conf]
  796. Fernando Corinto, Valentina Lanza, Marco Gilli
    Limit Cycles and Bifurcations in Nonlinear Oscillatory Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3163-3166 [Conf]
  797. Michele Bonnin, Fernando Corinto, Marco Gilli, Pier Paolo Civalleri
    Small Amplitude, Phase Locked Response in Oscillatory Networks with Delays. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3167-3170 [Conf]
  798. Stanley Y. M. Lam, Bertram Emil Shi
    Active Visual Tracking of Heading Direction By Combining Motion Energy Neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3171-3174 [Conf]
  799. Shingo Yoshizawa, Yoshikazu Miyanaga
    Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3175-3178 [Conf]
  800. Dengwei Fu
    A Low-Cost Phase-Noise Cancellation Method for OFDM Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3179-3182 [Conf]
  801. Chen Meng, Jamal Tuqan
    Fractionally Spaced Orthogonal Frequency Division Multiplexing Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3183-3186 [Conf]
  802. Francois Nougarou, Messaoud Ahmed-Ouameur, Daniel Massicotte
    Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems: Part I - Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3187-3190 [Conf]
  803. T. Anil Kumar, K. Deergha Rao
    Breakdown Point Analysis of a New M-Estimator for Robust Multiuser Detection in Non-Gaussian Channels. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3191-3194 [Conf]
  804. Yunhua Wang, Linda DeBrunner, Dayong Zhou, Victor E. DeBrunner
    A Multiplier Structure Based on a Novel Real-time CSD Recoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3195-3198 [Conf]
  805. A. Abdelgawad, Magdy Bayoumi
    High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3199-3202 [Conf]
  806. Soo-Chang Pei, Jian-Jiun Ding
    Scaled Lifting Scheme and Generalized Reversible Integer Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3203-3206 [Conf]
  807. S. Chandrasekaran, A. Amira
    Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix Transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3207-3210 [Conf]
  808. G. L. Bernocchi, Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
    Low-power adaptive filter based on RNS components. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3211-3214 [Conf]
  809. Mohamed H. Abu-Rahma, Mohab Anis
    Variability in VLSI Circuits: Sources and Design Considerations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3215-3218 [Conf]
  810. Yehia Massoud, Arthur Nieuwoudt, Tamer Ragheb
    Variability-Aware Synthesis for Wideband Low Noise Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3219-3222 [Conf]
  811. Ja Chun Ku, Yehea I. Ismail
    Attaining Thermal Integrity in Nanometer Chips. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3223-3226 [Conf]
  812. Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
    Substrate Noise Reduction Based On Noise Aware Cell Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3227-3230 [Conf]
  813. Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu
    Leakage-Aware Design of Nanometer SoC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3231-3234 [Conf]
  814. Yong Hu, Joseph Mak, Hongtao Liu, Keith D. K. Luk
    ECG Cancellation for Surface Electromyography Measurement Using Independent Component Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3235-3238 [Conf]
  815. Feng Wan, Wei-Ping Zhu, M. N. S. Swamy
    Linear Prediction Based Semi-Blind Channel Estimation for MIMO-OFDM System. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3239-3242 [Conf]
  816. Wai Yie Leong, Danilo P. Mandic
    Noisy Component Extraction (Noice). [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3243-3246 [Conf]
  817. Hiroshi Sawada, Shoko Araki, Shoji Makino
    Measuring Dependence of Bin-wise Separated Signals for Permutation Alignment in Frequency-domain BSS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3247-3250 [Conf]
  818. Ke Deng, Qinye Yin, Huiming Wang
    Closed Form Parameters Estimation for Near Field Sources. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3251-3254 [Conf]
  819. Massimo Alioto, Gaetano Palumbo
    Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3255-3258 [Conf]
  820. A. Neslin Ismailoglu, Murat Askar
    Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3259-3262 [Conf]
  821. Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
    Digital Multiplication using Continuous Valued Digits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3263-3266 [Conf]
  822. Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng
    An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3267-3270 [Conf]
  823. Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
    Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3271-3274 [Conf]
  824. Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta
    A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3275-3278 [Conf]
  825. Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta
    A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3279-3282 [Conf]
  826. Minsik Ahn, Chang-ho Lee, Joy Laskar
    CMOS High Power SPDT Switch using Multigate Structure. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3283-3286 [Conf]
  827. Sohrab Samadian
    A Low Phase Noise Quad-Band CMOS VCO with Minimized Gain Variation for GSM/GPRS/EDGE. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3287-3290 [Conf]
  828. Khurram Waheed, Robert B. Staszewski, John L. Wallberg
    Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3291-3294 [Conf]
  829. Kofi M. Odame, Paul E. Hasler
    An Adaptive Quality-Factor Bandpass Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3295-3298 [Conf]
  830. Jader A. De Lima
    A Compact On-Chip Capacitive-Coupling Scheme for Very-Low Frequency Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3299-3302 [Conf]
  831. A. G. Katsiamis, H. M. D. Ip, Emmanuel M. Drakakis
    A Practical CMOS Companding Sinh Lossy Integrator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3303-3306 [Conf]
  832. Xi Zhu, Yichuang Sun, James Moritz
    A 0.18µm CMOS 300MHz Current-Mode LF Seventh-order Linear Phase Filter for Hard Disk Read Channels. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3307-3310 [Conf]
  833. Mladen Vucic, Goran Molnar
    Design of Systems with Prescribed Impulse Response Based on Second-Order Cone Programming. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3311-3314 [Conf]
  834. R. G. Bolea, A. Luque, J. M. Quero
    Single-Wafer Pressure Capacitive Sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3315-3318 [Conf]
  835. Jaume Verd, Arantxa Uranga, Jordi Teva, Gabriel Abadal, F. Torres, Nuria Barniol, Francesc Pérez-Murano, Jaume Esteve
    CMOS Cantilever-based Oscillator for Attogram Mass Sensing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3319-3322 [Conf]
  836. Z. Cai, J. Hao, S. Takahashi, J. H. Ng, Y. Gong, P. Varghese
    Simultaneous Measurement of Temperature and Lateral Force Using an Arc-Shaped FBG Sensor Module. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3323-3326 [Conf]
  837. Pablo Ituero, José L. Ayala, Marisa López-Vallejo
    Leakage-based On-Chip Thermal Sensor for CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3327-3330 [Conf]
  838. Leila Shepherd, Pantelis Georgiou, Chris Toumazou
    A novel voltage-clamped CMOS ISFET sensor interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3331-3334 [Conf]
  839. Retdian A. Nicodimus, Shigetaka Takagi, Nobuo Fujii
    Improvement of Bootstrapped Switch using Track and Precharge Phase. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3335-3338 [Conf]
  840. Dongwon Seo, Yuhua Guo, Manu Mishra
    High-Voltage Analog Circuit Design using Thin-Oxide MOS Devices only. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3339-3342 [Conf]
  841. R. Chebli, Mohamad Sawan, Yvon Savaria, Kamal El-Sankary
    High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3343-3346 [Conf]
  842. Reza Navid, Thomas H. Lee, Robert W. Dutton
    A Circuit-Based Noise Parameter Extraction Technique for MOSFETs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3347-3350 [Conf]
  843. Jeffrey S. Walling, David J. Allstot
    Monolithic Spiral Transformers: A Design Methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3351-3354 [Conf]
  844. Sylvie Renaud, Jean Tomas, Yannick Bornat, Adel Daouzli, Sylvain Saïghi
    Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3355-3358 [Conf]
  845. Paul E. Hasler, Scott Kozoil, Ethan Farquhar, Arindam Basu
    Transistor Channel Dendrites implementing HMM classifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3359-3362 [Conf]
  846. Kai M. Hynna, Kwabena Boahen
    Silicon neurons that burst when primed. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3363-3366 [Conf]
  847. Johannes Schemmel, Daniel Brüderle, Karlheinz Meier, Boris Ostendorf
    Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3367-3370 [Conf]
  848. Giacomo Indiveri, Stefano Fusi
    Spike-based learning in VLSI networks of integrate-and-fire neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3371-3374 [Conf]
  849. Stefan Mendel, Christian Vogel
    On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3375-3378 [Conf]
  850. Soon-Ik Cho, Suki Kim, Shin-Il Lim, Kwang-Hyun Baek
    A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3379-3382 [Conf]
  851. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Improved Background Algorithms for Pipeline ADC Full Calibration. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3383-3386 [Conf]
  852. Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
    A distortion model for pipeline Analog-to-Digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3387-3390 [Conf]
  853. Jingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yongming Li, Zhihua Wang
    A Pipelined A/D Conversion Technique with Low INL and DNL. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3391-3394 [Conf]
  854. Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu
    Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3395-3398 [Conf]
  855. Satoshi Tayu, Shuichi Ueno
    On the Complexity of Three-Dimensional Channel Routing (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3399-3402 [Conf]
  856. Masaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura
    Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3403-3406 [Conf]
  857. Gaurav Trivedi, H. Narayanan
    Application of Fast DC Analysis to Partitioning Hypergraphs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3407-3410 [Conf]
  858. Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou
    Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3411-3414 [Conf]
  859. Wen-Chung Kao, Hong-Shuo Tai, Chia-Pin Shen, Jia-An Ye, Hong-Fa Ho
    A Pipelined Architecture Design for Trilateral Noise Filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3415-3418 [Conf]
  860. Jin-Sung Kim, Hyuk-Jae Lee
    A PDP Sub-field Coding Algorithm for the Reduction of Errors due to Line Load Variation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3419-3422 [Conf]
  861. Yasser Ismail, Mohsen Shaaban, Magdy Bayoumi
    An Adaptive Block Size Phase Correlation Motion Estimation Using Adaptive Early Search Termination Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3423-3426 [Conf]
  862. Wei Ping, Li Junli, Lu Dongming, Chen Gang
    A Fast and reliable switching median filter for highly corrupted images by impulse noise. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3427-3430 [Conf]
  863. Jin Xu, Jinghuo Guan, Xingdong Wang, Jun Sun, Guangtao Zhai, Zhengguo Li
    An OWE-based Algorithm for Line Scratches Restoration in Old Movies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3431-3434 [Conf]
  864. Tian-Bo Deng
    High-Speed and Low-Cost Structures for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3435-3438 [Conf]
  865. Juha Yli-Kaakinen, Tapio Saramäki
    A Simplified Structure for FIR Filters with an Adjustable Fractional Delay. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3439-3442 [Conf]
  866. Soo-Chang Pei, Huei-Shan Lin, Peng-Hua Wang
    Design of Allpass Fractional Delay Filter and Fractional Hilbert Transformer Using Closed-Form of Cepstral Coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3443-3446 [Conf]
  867. C. C. Tseng
    Closed-Form Design of Variable Fractional Order Integrator Using Complex Cepstrum. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3447-3450 [Conf]
  868. S. Vijay, A. Prasad Vinod, Edmund Ming-Kit Lai
    A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3451-3454 [Conf]
  869. Thomas Schierl, Cornelius Hellge, Shpend Mirta, Karsten Gruneberg, Thomas Wiegand
    Using H.264/AVC-based Scalable Video Coding (SVC) for Real Time Streaming in Wireless IP Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3455-3458 [Conf]
  870. Chih-Wei Chiou, Chia-Ming Tsai, Chia-Wen Lin
    Fast Mode Decision Algorithms for Adaptive GOP Structure in the Scalable Extension of H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3459-3462 [Conf]
  871. Hung-Hui Juan, Hsiang-Chun Huang, ChingYao Huang, Tihao Chiang
    Scalable Video Streaming over Mobile WiMAX. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3463-3466 [Conf]
  872. Mattia C. O. Bogino, Pasquale Cataldi, Marco Grangetto, Enrico Magli, Gabriella Olmo
    Sliding-Window Digital Fountain Codes for Streaming of Multimedia Contents. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3467-3470 [Conf]
  873. Qibin Sun, Zhi Li, Yong Lian, Chang Wen Chen
    Joint Source-Channel-Authentication Resource Allocation for Multimedia overWireless Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3471-3474 [Conf]
  874. Maurice G. Bellanger
    On the Performance of Two Constant Modulus Algorithms in Equalization with non-CM Signals. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3475-3478 [Conf]
  875. Parthapratim De
    Combined Linear Prediction and Subspace Based Blind Equalizers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3479-3482 [Conf]
  876. Hiroki Matsumoto, Shuntaro Takasaki, Toshihiro Furukawa
    A proposal of a new blind equalizer using output signals of decision device. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3483-3485 [Conf]
  877. Mitsuru Kawamoto, Kiyotaka Kohno, Yujiro Inouye
    Eigenvector Algorithms for Blind Deconvolution of MIMO-IIR Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3486-3489 [Conf]
  878. Kiyotaka Kohno, Yujiro Inouye, Mitsuru Kawamoto
    A Matrix Pseudo-Inversion Lemma and Its Application to Block-Based Adaptive Blind Deconvolution for MIMO Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3490-3493 [Conf]
  879. Sung-Joon Jang, Moo-Kyoung Chung, Jaemoon Kim, Chong-Min Kyung
    Cache Miss-Aware Dynamic Stack Allocation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3494-3497 [Conf]
  880. Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa
    Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3498-3501 [Conf]
  881. Hou-Jen Ko, Chun-Jen Tsai
    A Double-Issue Java Processor Design for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3502-3505 [Conf]
  882. Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
    Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3506-3509 [Conf]
  883. Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao
    A Low-cost and High-performance SoC Design for OMA DRM2 Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3510-3513 [Conf]
  884. Stefano Marsili, Manfred Punzenberger
    Simple design equations of gain compression and distortion spectrum in broadband RF transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3514-3517 [Conf]
  885. C. Wicpalek, T. Mayer, L. Maurer, U. Vollenbruch, T. Pittorino, A. Springer
    Analysis of Spurious Emission and In-Band Phase Noise of an All Digital Phase Locked Loop for RF Synthesis using a Frequency Discriminator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3518-3521 [Conf]
  886. Stefano Marsili
    Technique for Peak to Average Power Ratio Reduction suited for M-carrier WCDMA Base Station Transmitters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3522-3525 [Conf]
  887. C. Litchfield, P. Lee, R. J. Langley, J. C. Batchelor
    Logarithmic Codecs for Adaptive Beamforming in WCDMA Downlink Channels. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3526-3529 [Conf]
  888. Andreas Burg, S. Haene, Wolfgang Fichtner, M. Rupp
    Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3530-3533 [Conf]
  889. Mikko Kaltiokallio, Saska Lindfors, Ville Saari, Jussi Ryynänen
    Design of Precise Gain GmC-leapfrog Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3534-3537 [Conf]
  890. Juan P. Alegre, Santiago Celma, Belén Calvo, J. M. Garcia del Pozo
    A Novel CMOS Envelope Detector Structure. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3538-3541 [Conf]
  891. Marcello De Matteis, Stefano D'Amico, Andrea Baschirotto
    A 600mV 3.6mW 68dB DR 4th Order Analog Base Band Filter for WLAN Receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3542-3545 [Conf]
  892. Ville Saari, Saska Lindfors
    Analysis of Common-Mode Induced Even-Order Distortion in a Pseudo-Differential gm-C Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3546-3549 [Conf]
  893. Shanthi Pavan
    Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3550-3553 [Conf]
  894. Bin Guo, Amine Bermak, Maxime Ambard, Dominique Martinez
    A 4×4 Logarithmic Spike Timing Encoding Scheme for Olfactory Sensor Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3554-3557 [Conf]
  895. Ndubuisi Ekekwe, Ralph Etienne-Cummings, Peter Kazanzides
    Incremental Encoder Based Position and Velocity Measurements VLSI Chip with Serial Peripheral Interface. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3558-3561 [Conf]
  896. Andrew Mason, Yue Huang, Chao Yang, Jichun Zhang
    Amperometric Readout and Electrode Array Chip for Bioelectrochemical Sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3562-3565 [Conf]
  897. Jina Kim, Benjamin L. Grisso, Dong S. Ha, Daniel J. Inman
    Digital Wideband Excitation Technique for Impedance-Based Structural Health Monitoring Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3566-3569 [Conf]
  898. Silvana Sanudo, Favio R. Masson, Pedro Julian
    Bounded state space particle filter for network sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3570-3573 [Conf]
  899. Jose M. Quero
    Voltage Elevator using a MEMS Resonator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3574-3577 [Conf]
  900. Clement Joseph, Mounir Boukadoum, Joe Charlson, David Starikov, Abdelhak Bensaoula
    High-speed front end for LED-Photodiode based fluorescence lifetime measurement system. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3578-3581 [Conf]
  901. Vincenzo Ferragina, Massimo Ferri, Marco Grassi, Andrea Baschirotto
    A 12.4 ENOB Incremental A/D Converter for High-Linearity Sensors Read-Out Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3582-3585 [Conf]
  902. Brian Gestner, Jason Tanner, David Anderson
    Glass Break Detector Analog Front-End Using Novel Classifier Circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3586-3589 [Conf]
  903. Fule Li, Zhihua Wang, Dongmei Li
    An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3590-3593 [Conf]
  904. Wen-Shen Chou, Shu-Chieh Yang, Fu-Lung Hsueh, Heng-Chang Huang, Chih-Ji Hsiao
    A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3594-3597 [Conf]
  905. Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire
    On-Line Histogram Equalization for Flash ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3598-3601 [Conf]
  906. J. P. Oliveira, J. Goes, B. Esperanca, N. Paulino, J. Fernandes
    Low-Power CMOS Comparator with Embedded Amplification for Ultra-high-speed ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3602-3605 [Conf]
  907. Takahide Sato, Shigetaka Takagi, Nobuo Fujii
    Low-power design technique for flash A/D converters based on reduction of the number of comparators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3606-3609 [Conf]
  908. Munkyo Seo, Sopan Joshi, Ian A. Young
    A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3610-3613 [Conf]
  909. Stijn Reekmans, Pieter Rombouts, Ludo Weyten
    Quadrature Mismatch Shaping Techniques for Fully Differential Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3614-3617 [Conf]
  910. Eric C. Moule, Zeljko Ignjatovic
    Blue-Noise Sigma-Delta Modulator: Improving Substrate Noise and Nonlinear Amplifier Gain Effects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3618-3621 [Conf]
  911. Liyuan Liu, Run Chen, Dongmei Li
    A 20-Bit Sigma-Delta D/A for Audio Applications in 0.13um CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3622-3625 [Conf]
  912. Bupesh Pandita, K. W. Martin
    Designing Complex Delta Sigma Modulators with Signal-Transfer Functions having Good Stop-Band Attenuation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3626-3629 [Conf]
  913. Zhenyu Wei, Hongliang Li, King Ngi Ngan
    An Efficient Intra Mode Selection Algorithm For H.264 Based On Fast Edge Classification. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3630-3633 [Conf]
  914. Zhibo Chen, Guoping Qiu, Yang Lu, Lihua Zhu, Quqing Chen, Xiaodong Gu, Charles Wang
    Improving Video Coding at Scene Cuts using Attention based Adaptive Bit Allocation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3634-3638 [Conf]
  915. Xuan Jing, Lap-Pui Chau
    Improved Frame Level MAD Prediction and Bit Allocation Scheme for H.264/AVC Rate Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3639-3642 [Conf]
  916. Xiang Li, Norbert Oertel, Andre Kaup
    Adaptive Lagrange Multiplier Selection for Intra-Frame Video Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3643-3646 [Conf]
  917. Hung-Ming Wang, Ji-Kun Lin, Jar-Ferr Yang
    Fast H.264 Inter Mode Decision Based on Inter and Intra Block Conditions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3647-3650 [Conf]
  918. Qichao Sun, Xin-Hao Chen, Xiaoyang Wu, Lu Yu
    A Content-adaptive Fast Multiple Reference Frames Motion Estimation in H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3651-3654 [Conf]
  919. Jang-Jer Tsai, Hsueh-Ming Hang
    A Genetic Rhombus Pattern Search for Block Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3655-3658 [Conf]
  920. Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto
    Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3659-3662 [Conf]
  921. Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan
    Low power variable block size motion estimation using pixel truncation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3663-3666 [Conf]
  922. Meng-chou Chang, Yong-Jie Cheng
    Motion Detection by Using Entropy Image and Adaptive State-Labeling Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3667-3670 [Conf]
  923. Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
    SAT-based ATPG for Path Delay Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3671-3674 [Conf]
  924. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3675-3678 [Conf]
  925. Chandan Giri, Santanu Chattopadhyay
    Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3679-3682 [Conf]
  926. Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li
    Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3683-3686 [Conf]
  927. Aijiao Cui, Chip-Hong Chang
    Watermarking for IP Protection through Template Substitution at Logic Synthesis Level. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3687-3690 [Conf]
  928. Mohamed A. Abd El ghany, Aly E. Salama, Ahmed H. Khalil
    Design and Implementation of FPGA-based Systolic Array for LZ Data Compression. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3691-3695 [Conf]
  929. Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan
    CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3696-3699 [Conf]
  930. Yaling Ma, Mingjie Lin
    Collaborative Routing Architecture for FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3700-3703 [Conf]
  931. Nicolas Farrugia, Franck Mamalet, Sébastien Roux, Fan Yang, Michel Paindavoine
    A Parallel Face Detection System Implemented on FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3704-3707 [Conf]
  932. Carlos Paiz, Boris Kettelhoit, Mario Porrmann
    A design framework for FPGA-based dynamically reconfigurable digital controllers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3708-3711 [Conf]
  933. Jun Wang, Ge Zhang, Weiwu Hu
    An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3712-3715 [Conf]
  934. Jingye Xu, Abinash Roy, Masud H. Chowdhury
    Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3716-3719 [Conf]
  935. Muhammad Arsalan, Maitham Shams
    Asynchronous Adiabatic Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3720-3723 [Conf]
  936. Rodrigo Jaramillo-Ramirez, Mohab Anis
    A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3724-3727 [Conf]
  937. Richard B. Wunderlich, Brian P. Degnan, Paul E. Hasler
    Capacitively-Biased Floating-Gate CMOS: a New Logic Family. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3728-3731 [Conf]
  938. Massimo Alioto, Gaetano Palumbo
    Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3732-3735 [Conf]
  939. Ja Chun Ku, Yehea I. Ismail
    A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3736-3739 [Conf]
  940. Chung-Yu Chang, Wei-Ben Yang, Ching-Ji Huang, Cheng-Hsing Chien
    New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3740-3743 [Conf]
  941. Martin Hansson, Atila Alvandpour
    Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3744-3747 [Conf]
  942. Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
    Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3748-3751 [Conf]
  943. Shengjyi Yang, Chijie Lin, Chiuyun Hung, Jiying Wu, Yiwen Wang
    Application-Specific Instruction Generation for SOC Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3752-3755 [Conf]
  944. Yi Xu, Zhiqiang Gao, Xiangqing He
    A Flexible Embedded SRAM IP Compiler. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3756-3759 [Conf]
  945. Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi
    A New Approach for Design and Verification of Transaction Level Models. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3760-3763 [Conf]
  946. Sung Dae Kim, Myung Hoon Sunwoo
    Low Power ASIP Architecture Optimization based on Target Application Profiling. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3764-3767 [Conf]
  947. Rubil Ahmadi
    A Hold Friendly Flip-Flop For Area Recovery. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3768-3771 [Conf]
  948. Amir M. Amiri, Abdelhakim Khouas, Mounir Boukadoum
    On the Timing Uncertainty in Delay-Line-based Time Measurement Applications Targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3772-3775 [Conf]
  949. Henrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux
    Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3776-3779 [Conf]
  950. Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin
    A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3780-3783 [Conf]
  951. DiaaEldin Khalil, Yehea I. Ismail
    Approximate Frequency Response Models for RLC Power Grids. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3784-3787 [Conf]
  952. Dongwon Seo, Yuhua Guo
    Mismatch Compensated Design Techniques under Packaging-Induced Die Stress. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3788-3791 [Conf]
  953. Tien-Yu Lo, Chung-Chih Hung
    1-V Linear CMOS Transconductor with 65 dB THD in Nano-Scale CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3792-3795 [Conf]
  954. Kyu-young Kim, Kwansu Shon, Soo-Won Kim, Jae-Tack Yoo
    Dual-Output Trans-Impedance Amplifier of Cost-effective CMOS Optical Receiver for Digital Audio Interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3796-3799 [Conf]
  955. T. M. Abdelrahman, Serdar Özoguz, Ahmed S. Elwakil
    New squaring circuit with reduced sensitivity to element mismatches using differentially driven translinear cells. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3800-3803 [Conf]
  956. Giuseppe de Vita, Giuseppe Iannaccone
    A 109 nW, 44 ppm/°C CMOS Current Reference with Low Sensitivity to Process Variations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3804-3807 [Conf]
  957. Jeonghun Kim, Kyu-sam Lim, Suki Kim
    Dynamic Eccentric Error Compensation for Track Following Control of Optical Disk Driver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3808-3811 [Conf]
  958. F. Yuan
    CMOS Gyrator-C Active Transformers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3812-3815 [Conf]
  959. David W. Graham, Paul E. Hasler
    Run-Time Programming of Analog Circuits Using Floating-Gate Transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3816-3819 [Conf]
  960. Sven Soell, Bernd Porr
    An Undersampling Digital Microphone. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3820-3823 [Conf]
  961. Francesco Cannillo, Chris Toumazou
    Fractional-Rate FM-to-Digital Delta-Sigma-Converters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3824-3827 [Conf]
  962. Liangguo Shen, Zushu Yan, Xing Zhang, Yuanfu Zhao, Yuan Wang
    Design of High-Performance Voltage Regulators Based on Frequency-Dependent Feedback Factor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3828-3831 [Conf]
  963. Savvas Koudounas, Julius Georgiou
    A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3832-3835 [Conf]
  964. Burak Kelleci, Aydin I. Karsilayan
    Low-Voltage Temperature-Independent Current Reference with no External Components. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3836-3839 [Conf]
  965. Luis Toledo, Walter Lancioni, Pablo Petrashin, Carlos Dualibe, Carlos Vazquez
    A new CMOS voltage reference scheme based on Vth-difference principle. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3840-3843 [Conf]
  966. Chia-Wei Chang, Tien-Yu Lo, Chia-Min Chen, Kuo-Hsi Wu, Chung-Chih Hung
    A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3844-3847 [Conf]
  967. Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su
    A Sub-1V Low-Power High-Speed Static Frequency Divider. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3848-3851 [Conf]
  968. Sang-Hyun Cho, Chang-Kyo Lee, Jong-In Song
    Design of a 1-Volt and µ-power SARADC for Sensor Network Application. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3852-3855 [Conf]
  969. Zhenying Luo, Sameer R. Sonkusale
    A Novel Low Power BPSK Demodulator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3856-3859 [Conf]
  970. Hanjun Jiang, Degang Chen, Randall L. Geiger
    Deterministic DEM DAC Performance Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3860-3863 [Conf]
  971. Richard Geisler, John Liobe, Martin Margala
    Process and Temperature Calibration of PLLs with BiST Capabilities. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3864-3867 [Conf]
  972. Carlos Muniz-Montero, Ramón González Carvajal, Alejandro Díaz-Sánchez, J. Miguel Rocha
    Low frequency, current mode programmable KHN filters using large-valued active resistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3868-3871 [Conf]
  973. Rui Xiao, Amit Laknaur, Haibo Wang
    A Fully Programmable Analog Window Comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3872-3875 [Conf]
  974. Athon Zanikopoulos, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund
    Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3876-3879 [Conf]
  975. Josep Soler Garrido, Robert J. Piechocki
    Analog Implementation of a Mean Field Detector for Multiple Antenna Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3880-3883 [Conf]
  976. Calogero D. Presti, Francesco Carrara, Antonino Scuderi, Giuseppe Palmisano
    Fast Peak Detector with Improved Accuracy and Linearity for High-Frequency Waveform Processing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3884-3887 [Conf]
  977. Chih-Hsing Lin, Ching-Te Chiu
    A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3888-3891 [Conf]
  978. Pei-Zong Rao, Tang-Yuan Chang, Ching-Piau Liang, Shyh-Jong Chung
    A Wideband CMOS Mixer with Feedforward Compensated Differential Transconductor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3892-3895 [Conf]
  979. Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani
    High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3896-3899 [Conf]
  980. Tongqiang Gao, Dongmei Li, Baoyong Chi, Zhihua Wang
    A CMOS class-E Power Amplifiers with Power Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3900-3903 [Conf]
  981. Mohsen Maadani, Seyed Mojtaba Atarodi
    A Low-Area, 0.18µm CMOS, 10Gb/s Optical Receiver Analog Front End. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3904-3907 [Conf]
  982. Naoyuki Unno, Takashi Fujita, Peter Lindberg, B. Siddik Yarman, Nobuo Fujii
    Dual Band Antenna Equalizer Realized by Utilizing 0.18µm Si-Processing Technology for a Pifa-900. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3908-3911 [Conf]
  983. Haiyong Wang, Guoliang Shou, Nanjian Wu
    A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3912-3915 [Conf]
  984. Alessio Cacciatori, Laura Lorenzi, Luigi Colalongo
    A Power Efficient HBT Pulse Generator for UWB Radars. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3916-3919 [Conf]
  985. Yanjie Wang, Anthony Ho, Kris Iniewski, Vincent Gaudet
    Inductive ESD Protection For Narrow Band and Ultra-Wideband CMOS Low Noise Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3920-3923 [Conf]
  986. Shuilong Huang, Zhihua Wang
    A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3924-3927 [Conf]
  987. Kunal Mukherjee, Bah-Hwee Gwee
    A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3928-3931 [Conf]
  988. Volker Mildner, Stefan Goetze, Karl-Dirk Kammeyer, Alfred Mertins
    Optimization of Gabor Features for Text-Independent Speaker Identification. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3932-3935 [Conf]
  989. Te-Hsueh Lai, Chung-Neng Wang, Tihao Chiang
    A NMR Optimized Bitrate Transcoder for MPEG-2/4 LC-AAC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3936-3939 [Conf]
  990. Arturo Camacho, John G. Harris
    A Pitch Estimation Algorithm Based on the Smooth Harmonic Average Peak-to-Valley Envelope. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3940-3943 [Conf]
  991. C. Shahnaz, Wei-Ping Zhu, M. Omair Ahmad
    An Approach for Voiced/Unvoiced Decision of Colored Noise-Corrupted Speech. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3944-3947 [Conf]
  992. Doo Hyun Choi, Ick Hoon Jang, Mi Hye Kim, Nam Chul Kim
    Color Image Enhancement Based on Single-Scale Retinex With a JND-Based Nonlinear Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3948-3951 [Conf]
  993. An-Chao Tsai, Anand Paul, Jia-Ching Wang, Jhing-Fa Wang
    Efficient Intra Prediction in H.264 Based on Intensity Gradient Approach. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3952-3955 [Conf]
  994. Tian Song, Kazuhiro Ogata, Kosuke Saito, Takashi Shimamoto
    Adaptive Search Range Motion Estimation Algorithm for H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3956-3959 [Conf]
  995. Ibrahim Karliga, Jenq-Neng Hwang
    Extraction and Integration of Human Body Parts for 3-D Motion Analysis of Golf Swing from Single-Camera Video Sequences. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3960-3963 [Conf]
  996. Zhengming Fu, Eugenio Culurciello
    A 3D Integrated Feature-Extracting Image Sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3964-3967 [Conf]
  997. Vincent Brost, Fan Yang, Michel Paindavoine
    A modular VLIW Processor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3968-3971 [Conf]
  998. Henrik Svensson, Thomas Lenart, Viktor Öwall
    Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3972-3975 [Conf]
  999. Yu Hu, Qing Li, Siwei Ma, C. C. Jay Kuo
    Decoder-Friendly Adaptive Deblocking Filter (DF-ADF) Mode Decision in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3976-3979 [Conf]
  1000. Chengjun Zhang, Chunyan Wang, M. Omair Ahmad
    A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3980-3983 [Conf]
  1001. Jung-Wook Kim, Jinook Song, SeokHo Lee, In-Cheol Park
    Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3984-3987 [Conf]
  1002. Magdy T. Hanna
    On the Angular Decomposition Technique for Computing the Discrete Fractional Fourier Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3988-3991 [Conf]
  1003. George E. Antoniou
    2-D Tridiagonal IIR Filters/Systems: State Space and Circuit Realizations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3992-3995 [Conf]
  1004. Takao Hinamoto, Takuro Kawagoe
    Optimal Synthesis of State-Estimate Feedback Controllers with Minimum l2-Sensitivity and No Overflow Oscillations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3996-3999 [Conf]
  1005. An P. N. Vo, Truong T. Nguyen, Soontorn Oraintara
    Image Denoising using Shiftable Directional Pyramid and Scale Mixtures of Complex Gaussians. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:4000-4003 [Conf]
  1006. Beilei Huang, Edmund Ming-Kit Lai, A. Prasad Vinod
    Sampling at Minimum Sampling Rate for Signals in Shift Invariant Spaces. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:4004-4007 [Conf]
  1007. A. Lombardi, Edoardo Bonizzoni, Piero Malcovati, Franco Maloberti
    A Low Power Sinc3 Filter for Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:4008-4011 [Conf]
  1008. Jatan Shah, Rama Sangireddy
    Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:4012-4015 [Conf]
  1009. F. N. Martin Pirchio, P. Julian, Pablo Sergio Mandolesi, Alfonso Chacon-Rodriguez
    An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:4016-4019 [Conf]
  1010. Ümit Güz, Hakan Gürkan, B. Siddik Yarman
    A Novel Fast Algorithm for Speech and Audio Coding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:4020-4023 [Conf]
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