Conferences in DBLP
Jim Kahle Cell architecture: key physical design features and methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Johnson , Umesh Nawathe An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2). [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xiang , Liang Deng , Ruchir Puri , Kai-Yuan Chao , Martin D. F. Wong Dummy fill density analysis with coupling constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal Khandelwal , Ankur Srivastava Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xiang , Kai-Yuan Chao , Ruchir Puri , Martin D. F. Wong Is your layout density verification exact?: a fast exact algorithm for density calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Shiyan Hu , Jiang Hu Pattern sensitive placement for manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Takayuki Fukuoka , Akira Tsuchiya , Hidetoshi Onodera Worst-case delay analysis considering the variability of transistors and interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Ramalingam , Giri Devarayanadurg , David Z. Pan Accurate power grid analysis with behavioral transistor network modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Yiyu Shi , Lei He Empire: an efficient and compact multiple-parameterized model order reduction method. [Citation Graph (0, 0)][DBLP ] Conf ] Salim Chowdhury , John Lillis Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. [Citation Graph (0, 0)][DBLP ] Conf ] Jeegar Tilak Shah , Marius Evers , Jeff Trull , Alper Halbutogullari Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Louis Scheffer , Lars Liebmann , Riko Rakojcic , David White Rules vs tools: what's the right way to address IC manufacturing complexity? [Citation Graph (0, 0)][DBLP ] Conf ] Azad Naeemi , James D. Meindl Carbon nanotube interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Ray T. Chen Optical interconnects: a viable solution for interconnection beyond 10 gbit/sec. [Citation Graph (0, 0)][DBLP ] Conf ] Tung-Chieh Chen , Yi-Lin Chuang , Yao-Wen Chang X-architecture placement based on effective wire models. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Chong , Christian Szegedy A morphing approach to address placement stability. [Citation Graph (0, 0)][DBLP ] Conf ] Zhong Xiu , Rob A. Rutenbar Mixed-size placement with fixed macrocells using grid-warping. [Citation Graph (0, 0)][DBLP ] Conf ] Jianhua Li , Laleh Behjat , Jie Huang An effective clustering algorithm for mixed-size placement. [Citation Graph (0, 0)][DBLP ] Conf ] Song Chen , Takeshi Yoshimura A stable fixed-outline floorplanning method. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Wei Lin , Szu-Yu Chen , Chi-Feng Li , Yao-Wen Chang , Chia-Lin Yang Efficient obstacle-avoiding rectilinear steiner tree construction. [Citation Graph (0, 0)][DBLP ] Conf ] Renato Fernandes Hentschke , Jaganathan Narasimham , Marcelo O. Johann , Ricardo Augusto da Luz Reis Maze routing steiner trees with effective critical sink optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Fan Mo , Robert K. Brayton Semi-detailed bus routing with variation reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Keith So Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew A. Smith , Lars A. Schreiner , Erich Barke , Volker Meyer zu Bexten Algorithms for automatic length compensation of busses in analog integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gi-Joon Nam , Mehmet Can Yildiz , David Z. Pan , Patrick H. Madden ISPD placement contest updates and ISPD 2007 global routing contest. [Citation Graph (0, 0)][DBLP ] Conf ] Noel Menezes The good, the bad, and the statistical. [Citation Graph (0, 0)][DBLP ] Conf ] Chandu Visweswariah Fear, uncertainty and statistics. [Citation Graph (0, 0)][DBLP ] Conf ] Shankar Krishnamoorthy Variation and litho driven physical implementation system. [Citation Graph (0, 0)][DBLP ] Conf ] David Cross , Eric Nequist , Louis Scheffer A DFM aware, space based router. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Yu , Yu Hu , Chunchen Liu , Lei He Minimal skew clock embedding considering time variant temperature gradient. [Citation Graph (0, 0)][DBLP ] Conf ] Rupesh S. Shelar An efficent clustering algorithm for low power clock tree synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Cobb , Rajesh Garg , Sunil P. Khatri A methodology for interconnect dimension determination. [Citation Graph (0, 0)][DBLP ] Conf ] 