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Conferences in DBLP
- Pratibha Permandla, Michael Roberson, Chandrasekhar Boyapati
A type system for preventing data races and deadlocks in the java virtual machine language: 1. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:10- [Conf]
- Tai-Yi Huang, Pin-Chuan Chou, Cheng-Han Tsai, Hsin-An Chen
Automated fault localization with statistically suspicious program states. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:11-20 [Conf]
- Xiliang Zhong, Cheng-Zhong Xu
Frequency-aware energy optimization for real-time periodic and aperiodic tasks. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:21-30 [Conf]
- Yifan Zhu, Frank Mueller
DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:31-40 [Conf]
- Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Rusu, Ruibin Xu, Frank Liberato, Bruce R. Childers, Daniel Mossé, Rami G. Melhem
Integrated CPU and l2 cache voltage scaling using machine learning. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:41-50 [Conf]
- Joshua S. Auerbach, David F. Bacon, Daniel T. Iercan, Christoph M. Kirsch, V. T. Rajan, Harald Roeck, Rainer Trummer
Java takes flight: time-portable real-time programming with exotasks. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:51-62 [Conf]
- SungHyun Hong, Jin-Chul Kim, Jin Woo Shin, Soo-Mook Moon, Hyeong-Seok Oh, Jaemok Lee, Hyung-Kyu Choi
Java client ahead-of-time compiler for embedded systems. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:63-72 [Conf]
- Christophe Alias, Fabrice Baray, Alain Darte
Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:73-82 [Conf]
- Richard Vincent Bennett, Alastair Colin Murray, Björn Franke, Nigel P. Topham
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:83-92 [Conf]
- Minwook Ahn, Jooyeon Lee, Yunheung Paek
Optimistic coalescing for heterogeneous register architectures. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:93-102 [Conf]
- Florent Bouchez, Alain Darte, Fabrice Rastello
On the complexity of spill everywhere under SSA form. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:103-112 [Conf]
- Weifeng Xu, Russell Tessier
Tetris: a new register pressure control technique for VLIW processors. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:113-122 [Conf]
- Filip Pizlo, Antony L. Hosking, Jan Vitek
Hierarchical real-time garbage collection. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:123-133 [Conf]
- Kathryn M. O'Brien
Issues and challenges in compiling for the CBEA. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:134- [Conf]
- Daniel Kästner
Safe worst-case execution time analysis by abstract interpretation of executable code. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:135- [Conf]
- Jonathan Engelsma
Enabling seamless mobility: an enablers, experiences and tools perspective. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:136- [Conf]
- Po-Kuan Huang, Matin Hashemi, Soheil Ghiasi
Joint throughput and energy optimization for pipelined execution of embedded streaming applications. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:137-139 [Conf]
- Hansu Cho, Samar Abdi, Daniel Gajski
Interface synthesis for heterogeneous multi-core systems from transaction level models. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:140-142 [Conf]
- Ines Viskic, Samar Abdi, Daniel D. Gajski
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:143-145 [Conf]
- Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee
Enabling compiler flow for embedded VLIW DSP processors with distributed register files. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:146-148 [Conf]
- Karsten Walther, René Herzog, Jörg Nolte
Analyzing the real-time behaviour of deeply embedded event driven systems. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:149-151 [Conf]
- Joel Coffman, Christopher A. Healy, Frank Mueller, David B. Whalley
Generalizing parametric timing analysis. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:152-154 [Conf]
- Guangyu Chen, Feihui Li, Mahmut T. Kandemir
Compiler-directed application mapping for NoC based chip multiprocessors. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:155-157 [Conf]
- Shan Yan, Bill Lin
Stream execution on wide-issue clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:158-160 [Conf]
- Michael L. Chu, Scott A. Mahlke
Code and data partitioning for fine-grain parallelism. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:161-164 [Conf]
- Stephen Roderick Hines, Gary S. Tyson, David B. Whalley
Addressing instruction fetch bottlenecks by using an instruction register file. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:165-174 [Conf]
- Jun Yan, Wei Zhang
WCET analysis of instruction caches with prefetching. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:175-184 [Conf]
- Ke Ning, David R. Kaeli
External memory page remapping for embedded multimedia systems. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:185-194 [Conf]
- Hyungmin Cho, Bernhard Egger, Jaejin Lee, Heonshik Shin
Dynamic data scratchpad memory management for a memory subsystem with an MMU. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:195-206 [Conf]
- Lian Li 0002, Quan Hoang Nguyen, Jingling Xue
Scratchpad allocation for data aggregates in superperfect graphs. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:207-216 [Conf]
- Jihyun In, Ilhoon Shin, Hyojun Kim
SWL: a search-while-load demand paging scheme with NAND flash memory. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:217-226 [Conf]
- Qin Wang, Junpu Chen, Weihua Zhang, Min Yang, Binyu Zang
Optimizing software cache performance of packet processing applications. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:227-236 [Conf]
- Rajiv Ravindran, Michael Chu, Scott A. Mahlke
Compiler-managed partitioned data caches for low power. [Citation Graph (0, 0)][DBLP]
LCTES, 2007, pp:237-247 [Conf]
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