Conferences in DBLP
Ivan Radojevic , Zoran A. Salcic , Partha S. Roop McCharts and Multiclock FSMs for modeling large scale systems. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Hong Li , Rebecca L. Collins , Sampada Sonalkar , Luca P. Carloni Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design. [Citation Graph (0, 0)][DBLP ] Conf ] Xavier Leroy Formal verification of an optimizing compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Yi Lv , Huimin Lin , Hong Pan Computing Invariants for Parameter Abstraction. [Citation Graph (0, 0)][DBLP ] Conf ] Rathijit Sen , Y. N. Srikant Executable Analysis using Abstract Interpretation with Circular Linear Progressions. [Citation Graph (0, 0)][DBLP ] Conf ] Nirav Dave , Arvind , Michael Pellauer Scheduling as Rule Composition. [Citation Graph (0, 0)][DBLP ] Conf ] Deepak Mathaikutty , Sandeep K. Shukla Type Inference for IP Composition. [Citation Graph (0, 0)][DBLP ] Conf ] Man Cheuk Ng , Muralidaran Vijayaraghavan , Nirav Dave , Arvind , Gopal Raghavan , Jamey Hicks From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Edgar G. Daylight , Sandeep K. Shukla Local Causal Reasoning of a Safety-Critical Subway System. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Eveking , Martin Braun , Martin Schickel , Martin Schweikert , Volker Nimbler Multi-Level Assertion-Based Design. [Citation Graph (0, 0)][DBLP ] Conf ] Youngseok Oh , Danhyung Lee , Sungwon Kang , Jihyun Lee Extended Architecture Analysis Description Language for Software Product Line Approach in Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Forrest Brewer , James C. Hoe MEMOCODE 2007 Co-Design Contest. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Simpson , Pengyuan Yu , Patrick Schaumont , Sumit Ahuja , Sandeep K. Shukla VT Matrix Multiply Design for MEMOCODE '07. [Citation Graph (0, 0)][DBLP ] Conf ] Nirav Dave , Kermin Fleming , Myron King , Michael Pellauer , Muralidaran Vijayaraghavan Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Niemann , Christian Haubelt Towards a Unified Execution Model for Transactions in TLM. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Bombieri , Franco Fummi , Graziano Pravadelli , João Marques-Silva Towards Equivalence Checking Between TLM and RTL Models. [Citation Graph (0, 0)][DBLP ] Conf ] Yogesh S. Mahajan , Carven Chan , Ali Alphan Bayazit , Sharad Malik , Wei Qin Verification Driven Formal Architecture and Microarchitecture Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Bertrand Meyer Proving What Programs Do Not. [Citation Graph (0, 0)][DBLP ] Conf ] Bart D. Theelen , Oana Florescu , Marc Geilen , Jinfeng Huang , P. H. A. van der Putten , Jeroen Voeten Software/Hardware Engineering with the Parallel Object-Oriented Specification Language. [Citation Graph (0, 0)][DBLP ] Conf ] Wu Jigang , Thambipillai Srikanthan , Guang Chen One-dimensional Search Algorithms for Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Proshanta Saha , Tarek A. El-Ghazawi A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Geoffrey M. Brown , Lee Pike Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Eggersglüß , Görschwin Fey , Rolf Drechsler , Andreas Glowatz , Friedrich Hapke , Jürgen Schlöffel Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Hana Chockler , Ofer Strichman Easier and More Informative Vacuity Checks. [Citation Graph (0, 0)][DBLP ] Conf ] Byron Cook Bringing Hardware and Software Closer Together with Termination Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] 