Conferences in DBLP
Lazaros Papadopoulos , Dimitrios Soudris System-Level Application-Specific NoC Design for Network and Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Fournel , Antoine Fraboulet , Paul Feautrier Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Ioannis Panagopoulos , Christos Pavlatos , George Manis , George K. Papakonstantinou A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Julien Delorme An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Lai Mingche , Wang Zhiying , Guo Jianjun , Dai Kui , Shen Li Template Vertical Dictionary-Based Program Compression Scheme on the TTA. [Citation Graph (0, 0)][DBLP ] Conf ] Delong Shang , Chi-Hoon Shin , Ping Wang , Fei Xia , Albert Koelmans , Myeong-Hoon Oh , Seongwoon Kim , Alexandre Yakovlev Asynchronous Functional Coupling for Low Power Sensor Network Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Noureddine Chabini A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Saleh Abdel-Hafeez , Shadi M. Harb , William R. Eisenstadt Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports. [Citation Graph (0, 0)][DBLP ] Conf ] Yijun Liu , Pinghua Chen , Wenyan Wang , Zhenkun Li The Design and Implementation of a Power Efficient Embedded SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Björn Lipka , Ulrich Kleine Design of a Linear Power Amplifier with +/-1.5V Power Supply Using ALADIN. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Pugliese 0002 , Gregorio Cappuccino , Giuseppe Cocorullo Settling Time Minimization of Operational Amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Cosmin Popa Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Goel , Sarvesh Bhardwaj , Praveen Ghanta , Sarma B. K. Vrudhula Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] V. Migairou , Robin Wilson , S. Engels , Z. Wu , Nadine Azémard , Philippe Maurine A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Hsiung Hsu , Szu-Jui Chou , Jie-Hong Roland Jiang , Yao-Wen Chang A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Luo , Yu Wang , Ku He , Rong Luo , Huazhong Yang , Yuan Xie A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. [Citation Graph (0, 0)][DBLP ] Conf ] Marko Hoyer , Domenik Helms , Wolfgang Nebel Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. [Citation Graph (0, 0)][DBLP ] Conf ] Mandeep Singh , Christophe Giacomotto , Bart R. Zeydel , Vojin G. Oklobdzija Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. [Citation Graph (0, 0)][DBLP ] Conf ] C. R. Parthasarathy , A. Bravaix , C. Guérin , M. Denais , V. Huard Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Pandini , Guido A. Repetto , Vincenzo Sinisi Clock Distribution Techniques for Low-EMI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Mini Nanua , David Blaauw Crosstalk Waveform Modeling Using Wave Fitting. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Sato , Shiho Hagiwara , Takumi Uezono , Kazuya Masu Weakness Identification for Effective Repair of Power Distribution Network. [Citation Graph (0, 0)][DBLP ] Conf ] Prassanna Sithambaram , Alberto Macii , Enrico Macii New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Murgan , P. B. Bacinschi , Sujan Pandey , Alberto García Ortiz , Manfred Glesner On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Foad Dabiri , Ani Nahapetian , Miodrag Potkonjak , Majid Sarrafzadeh Soft Error-Aware Power Optimization Using Gate Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Grumer , Manuel Wendt , Christian Steger , Reinhold Weiss , Ulrich Neffe , Andreas Mühlberger Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Rosinger , Domenik Helms , Wolfgang Nebel RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating. [Citation Graph (0, 0)][DBLP ] Conf ] Allan Crone , Gabriel Chidolue Functional Verification of Low Power Designs at RTL. [Citation Graph (0, 0)][DBLP ] Conf ] Zoltán Herczeg , Ákos Kiss , Daniel Schmidt , Norbert Wehn , Tibor Gyimóthy XEEMU: An Improved XScale Power Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Maurice Keller , William P. Marnane Low Power Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Ruan , Zhiying Wang , Kui Dai , Yong Li Design and Test of Self-checking Asynchronous Control Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Behnam Ghavami , Hossein Pedram An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Alin Razafindraibe , Michel Robert , Philippe Maurine Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. [Citation Graph (0, 0)][DBLP ] Conf ] Michalis D. Galanis , Grigoris Dimitroulakos , Costas E. Goutis Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Hendrik Eeckhaut , Harald Devos , Dirk Stroobandt The Energy Scalability of Wavelet-Based, Scalable Video Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Peon-Quiros , Alexandros Bartzas , Stylianos Mamagkakis , Francky Catthoor , Jose Manuel Mendias , Dimitrios Soudris Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Sato , Yuji Kunitake Exploiting Input Variations for Energy Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Alin Razafindraibe , Philippe Maurine A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. [Citation Graph (0, 0)][DBLP ] Conf ] David Guerrero , Alejandro Millán , Jorge Juan-Chico , Manuel J. Bellido , Paulino Ruiz-de-Clavijo , Enrique Ostúa , J. Viejo Static Power Consumption in CMOS Gates Using Independent Bodies. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrice Guigues , Edith Kussener , Benjamin Duval , Hervé Barthélemy Moderate Inversion: Highlights for Low Voltage Design. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Teijiro Isokawa , Nobuyuki Matsui On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Raghavan , Nandhavel Sethubalasubramanian , Satyakiran Munaga , Estela Rey Ramos , Murali Jayapala , Oliver Weiss , Francky Catthoor , Diederik Verkest Semi Custom Design: A Case Study on SIMD Shufflers. [Citation Graph (0, 0)][DBLP ] Conf ] Ani Nahapetian , Foad Dabiri , Miodrag Potkonjak , Majid Sarrafzadeh Optimization for Real-Time Systems with Non-convex Power Versus Speed Models. [Citation Graph (0, 0)][DBLP ] Conf ] Harry I. A. Chen , Edward K. W. Loo , James B. Kuo , Marek Syrzycki Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Behnam Ghavami , Mahtab Niknahad , Mehrdad Najibi , Hossein Pedram A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Paulo F. Butzen , André Inácio Reis , Chris H. Kim , Renato P. Ribas Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Lucarz , Marco Mattavelli A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Lipskoch , Karsten Albers , Frank Slomka Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolas Kroupis , Dimitrios Soudris Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate. [Citation Graph (0, 0)][DBLP ] Conf ] Francesco Centurelli , Luca Giancane , Mauro Olivieri , Giuseppe Scotti , Alessandro Trifiletti A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Oscar Gustafsson , Saeeid Tahmasbi Oskuii , Kenny Johansson , Per Gunnar Kjeldsberg Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data. [Citation Graph (0, 0)][DBLP ] Conf ] Jon Alfredsson , Snorre Aunet Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. [Citation Graph (0, 0)][DBLP ] Conf ] Ch. Basetas , I. Kouretas , Vassilis Paliouras Low-Power Digital Filtering Based on the Logarithmic Number System. [Citation Graph (0, 0)][DBLP ] Conf ] Sylvain Miermont , Pascal Vivet , Marc Renaudin A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Henrik Eriksson Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] J. M. Daga Design and Industrialization Challenges of Memory Dominated SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Pandini Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] C. Svensson Analog Power Modelling. [Citation Graph (0, 0)][DBLP ] Conf ] F. Dahlgren Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] A. Emrich System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] 