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Conferences in DBLP

SAMOS Workshops (samos)
2007 (conf/samos/2007)

  1. Willie Anderson
    Software Is the Answer But What Is the Question? [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:1- [Conf]
  2. Jos Huisken
    Integrating VLIW Processors with a Network on Chip. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:2- [Conf]
  3. Taewook Oh, Youngmin Yi, Soonhoi Ha
    Communication Architecture Simulation on the Virtual Synchronization Framework. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:3-12 [Conf]
  4. Max R. de O. Schultz, Alexandre K. I. Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. dos Santos
    A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:13-23 [Conf]
  5. Sangsoo Park, Heonshik Shin
    Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:24-33 [Conf]
  6. Ka Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, Michel P. Schellekens
    SC2SCFL: Automated SystemC to SystemCFL Translation. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:34-45 [Conf]
  7. Seungjae Baek, Jongmoo Choi, Donghee Lee, Sam H. Noh
    Model and Validation of Block Cleaning Cost for Flash Memory. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:46-54 [Conf]
  8. Sungchan Park, Chao Chen, Hong Jeong
    VLSI Architecture for MRF Based Stereo Matching. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:55-64 [Conf]
  9. Teemu Pitkänen, Tero Partanen, Jarmo Takala
    Low-Power Twiddle Factor Unit for FFT Computation. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:65-74 [Conf]
  10. Pepijn J. de Langen, Ben H. H. Juurlink
    Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:75-85 [Conf]
  11. José O. Carlomagno Filho, Luiz F. P. Santos, Luiz C. V. dos Santos
    An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:86-95 [Conf]
  12. Norbert Esser, Renga Sundararajan, Joachim Trescher
    Improving TriMedia Cache Performance by Profile Guided Code Reordering. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:96-106 [Conf]
  13. Paul Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé
    A Streaming Machine Description and Programming Model. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:107-116 [Conf]
  14. Bastian Ristau, Gerhard Fettweis
    Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:117-126 [Conf]
  15. Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg
    Strategies for Compiling µ TC to Novel Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:127-138 [Conf]
  16. Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit
    Image Quantisation on a Massively Parallel Embedded Processor. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:139-148 [Conf]
  17. Michael G. Benjamin, David R. Kaeli
    Stream Image Processing on a Dual-Core Embedded System. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:149-158 [Conf]
  18. Marco Lanuzza, Stefania Perri, Pasquale Corsonello
    MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:159-168 [Conf]
  19. Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt
    FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:169-178 [Conf]
  20. Ari Kulmala, Erno Salminen, Timo D. Hämäläinen
    Evaluating Large System-on-Chip on Multi-FPGA Platform. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:179-189 [Conf]
  21. Hartwig Jeschke
    Efficiency Measures for Multimedia SOCs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:190-199 [Conf]
  22. Je-Hoon Lee, Young-Sin Cho, Seok-Man Kim, Kyoung-Rok Cho
    On-Chip Bus Modeling for Power and Performance Estimation. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:200-210 [Conf]
  23. Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frédéric Robert
    A Framework Introducing Model Reversibility in SoC Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:211-221 [Conf]
  24. Mark Thompson, Andy D. Pimentel
    Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:222-232 [Conf]
  25. Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala
    Resource Conflict Detection in Simulation of Function Unit Pipelines. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:233-240 [Conf]
  26. Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch
    A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:241-250 [Conf]
  27. Humberto Calderon, Carlo Galuzzi, Georgi Gaydadjiev, Stamatis Vassiliadis
    High-Bandwidth Address Generation Unit. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:251-262 [Conf]
  28. Sascha Uhrig, Jörg Mische, Theo Ungerer
    An IP Core for Embedded Java Systems. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:263-272 [Conf]
  29. Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala
    Parallel Memory Architecture for TTA Processor. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:273-282 [Conf]
  30. Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis
    A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:283-293 [Conf]
  31. Nainesh Agarwal, Nikitas J. Dimopoulos
    Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:294-303 [Conf]
  32. Paolo Bonzini, Dilek Harmanci, Laura Pozzi
    A Study of Energy Saving in Customizable Processors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:304-312 [Conf]
  33. John Glossner, Daniel Iancu, Mayan Moudgill, Michael Schulte, Stamatis Vassiliadis
    Trends in Low Power Handset Software Defined Radio. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:313-321 [Conf]
  34. Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor
    Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:322-332 [Conf]
  35. Anders Nilsson, Dake Liu
    Area Efficient Fully Programmable Baseband Processors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:333-342 [Conf]
  36. Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner
    The Next Generation Challenge for Software Defined Radio. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:343-354 [Conf]
  37. Chia-han Lee, Wayne Wolf
    Design Methodology for Software Radio Systems. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:355-364 [Conf]
  38. Tseesuren Batsuuri, Je-Hoon Lee, Kyoung-Rok Cho
    Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:365-374 [Conf]
  39. Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas
    A Comparative Study of Different FFT Architectures for Software Defined Radio. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:375-384 [Conf]
  40. Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen
    Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:385-395 [Conf]
  41. Mauri Kuorilehto, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen
    Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:396-407 [Conf]
  42. Aubin Lecointre, Daniela Dragomirescu, Robert Plana
    System Architecture Modeling of an UWB Receiver for Wireless Sensor Network. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:408-420 [Conf]
  43. Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta
    An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:421-430 [Conf]
  44. Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen
    SensorOS: A New Operating System for Time Critical WSN Applications. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:431-442 [Conf]
  45. Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen
    Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:443-453 [Conf]
  46. Dong-Min Son, Young-Bae Ko
    k + Neigh : An Energy Efficient Topology Control for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:454-463 [Conf]
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