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Conferences in DBLP

SAMOS Workshops (samos)
2007 (conf/samos/2007ic)

  1. Peter Westermann, Ludwig Schwoerer, Andre Kaufmann
    Applying Data Mapping Techniques to Vector DSPs. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:1-8 [Conf]
  2. Michael Med, Andreas Krall
    Instruction Set Encoding Optimization for Code Size Reduction. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:9-17 [Conf]
  3. Martin Thuresson, Magnus Själander, Magnus Bjork, Lars Svensson, Per Larsson-Edefors, Per Stenström
    FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:18-25 [Conf]
  4. Vassilis Papaefstathiou, Dionisios N. Pnevmatikatos, Manolis Marazakis, Giorgos Kalokairinos, Aggelos Ioannou, Michael Papamichael, Stamatis Kavadias, Giorgos Mihelogiannakis, Manolis Katevenis
    Prototyping Efficient Interprocessor Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:26-33 [Conf]
  5. Christoforos Kachris, Stamatis Vassiliadis
    Design Space Exploration of Configuration Manager for Network Processing Applications. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:34-40 [Conf]
  6. Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch
    Design Space Exploration of Media Processors: A Parameterized Scheduler. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:41-49 [Conf]
  7. Ganghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi
    Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:50-57 [Conf]
  8. Lazaros Papadopoulos, Christos Baloukas, Nikolaos Zompakis, Dimitrios Soudris
    Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:58-65 [Conf]
  9. Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero
    On the Problem of Minimizing Workload Execution Time in SMT Processors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:66-73 [Conf]
  10. Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek
    Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:74-81 [Conf]
  11. Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
    An Interrupt Controller for FPGA-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:82-87 [Conf]
  12. Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert
    Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:88-95 [Conf]
  13. Sergio A. Cuenca, Antonio Martinez, Antonio Jimeno, Jose Luis Sanchez
    A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe Machining. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:96-102 [Conf]
  14. Tero Rintaluoma, Olli Silvén
    Energy efficiency of mobile video decoding. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:103-109 [Conf]
  15. Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis
    Instruction-Level Fault Tolerance Configurability. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:110-117 [Conf]
  16. Benoît Garbinato, Rachid Guerraoui, Jarle Hulaas, Alexei Kounine, Maxime Monod, Jesper Honig Spring
    The Weight-Watcher Service and its Lightweight Implementation. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:118-127 [Conf]
  17. Kehuai Wu, Jan Madsen
    COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:128-136 [Conf]
  18. Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
    Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:137-144 [Conf]
  19. Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo
    An Evolutionary Approach to Area-Time Optimization of FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:145-152 [Conf]
  20. Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
    The ARISE Reconfigurable Instruction Set Extensions Framework. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:153-160 [Conf]
  21. Joachim Keinert, Christian Haubelt, Jürgen Teich
    Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:161-168 [Conf]
  22. Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
    Online Prediction of Applications Cache Utility. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:169-177 [Conf]
  23. Ezequiel Herruzo, Emilio L. Zapata, Oscar G. Plata
    Maximum and Sorted Cache Occupation Using Array Padding. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:178-185 [Conf]
  24. Vassilis Dimopoulos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos
    A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:186-193 [Conf]
  25. Nele Mentens, Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:194-200 [Conf]
  26. Sascha Muhlbach, Sebastian Wallner
    Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:201-208 [Conf]
  27. Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
    A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:209-214 [Conf]
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