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Conferences in DBLP

SAMOS Workshops (samos)
2006 (conf/samos/2006ic)

  1. Eero Aho, Jarno Vanne, Timo D. Hämäläinen
    Parallel Memory Implementation for Arbitrary Stride Accesses. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:1-6 [Conf]
  2. Shaahin Hessabi, Mehdi Modarressi, Maziar Goudarzi, Hani JavanHemmat
    A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:7-13 [Conf]
  3. Shuai Wang, Jie Hu, Sotirios G. Ziavras
    On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:14-20 [Conf]
  4. Francisco J. Villa, Manuel E. Acacio, José M. García
    On the Evaluation of Dense Chip-Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:21-27 [Conf]
  5. Mafijul Islam, Per Stenström
    Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:28-34 [Conf]
  6. Kashif Ali, Mokhtar Aboelaze, Suprakash Datta
    Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:35-42 [Conf]
  7. Sébastien Lafond, Johan Lilius
    Static Energy Saving Through Multi-Bank Memory Architecture. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:43-49 [Conf]
  8. Babak Salamat, Amirali Baniasadi, Kaveh Jokar Deris
    Area-Aware Optimizations for Resource Contrained Branch Predictors Exploited in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:50-55 [Conf]
  9. Hartwig Jeschke
    Design Space Expoloration Chip Size Estimation for SOC Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:56-62 [Conf]
  10. Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal
    Profiling Driven Scenarion Detection and Prediction for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:63-70 [Conf]
  11. Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas
    On the Calibration of Abstract Performance Models for System-level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:71-77 [Conf]
  12. Chantal Ykman-Couvreur, Vincent Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal
    Pareto-Based Application Specification for MP-SoC Customized Run-Time Management. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:78-84 [Conf]
  13. Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis
    Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:85-92 [Conf]
  14. Thilo Streichert, Christian Haubelt, Jürgen Teich
    Multi-Objective Topology Optimization for Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:93-98 [Conf]
  15. Rainer Schaffer, Renate Merker
    Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:99-106 [Conf]
  16. Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo
    Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:107-114 [Conf]
  17. Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti
    An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:115-122 [Conf]
  18. Hannes Muhr, Roland Höler
    Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:123-127 [Conf]
  19. Selim Gurun, Ye Wen, Navraj Chohan, Richard Wolski, Chandra Krintz
    SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:129-136 [Conf]
  20. Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya
    Memory-constrained Block Processing Optimization for Synthesis of DSP Software. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:137-143 [Conf]
  21. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:144-151 [Conf]
  22. Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf
    Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:152-159 [Conf]
  23. Stamatis Vassiliadis, Ioannis Sourdis
    FLUX Networks: Interconnects on Demand. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:160-167 [Conf]
  24. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    On-Chip Communication in Run-Time Assembled Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:168-176 [Conf]
  25. Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk
    Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:177-184 [Conf]
  26. Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
    Throughput optimization via cache partitioning for embedded multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:185-192 [Conf]
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