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Conferences in DBLP

System-Level Interconnect Prediction (slip)
2007 (conf/slip/2007)

  1. Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu
    Adaptable wire-length distribution with tunable occupation probability. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:1-8 [Conf]
  2. Payman Zarkesh-Ha, Ken Doniger
    Stochastic interconnect layout sensitivity model. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:9-14 [Conf]
  3. Taraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh
    Tutorial on congestion prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:15-24 [Conf]
  4. Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma
    An accurate and efficient probabilistic congestion estimation model in x architecture. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:25-32 [Conf]
  5. David Yeager, Darius Chiu, Guy G. Lemieux
    Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:33-40 [Conf]
  6. Alexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang
    Principle hessian direction based parameter reduction for interconnect networks with process variation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:41-46 [Conf]
  7. I-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang
    Statistical circuit optimization considering device andinterconnect process variations. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:47-54 [Conf]
  8. Avinoam Kolodny
    Networks on chips: keeping up with Rent's rule and Moore's law. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:55-56 [Conf]
  9. Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli
    Early wire characterization for predictable network-on-chip global interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:57-64 [Conf]
  10. Wim Heirman, Joni Dambre, Jan Van Campenhout
    Synthetic traffic generation as a tool for dynamic interconnect evaluation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:65-72 [Conf]
  11. Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand
    Impact of interconnect length changes on effective materials properties (dielectric constant). [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:73-80 [Conf]
  12. Hoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, Krishna Saraswat
    Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:81-88 [Conf]
  13. Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
    The nuts and bolts of physical synthesis. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:89-94 [Conf]
  14. Yu Hu, King Ho Tam, Tong Jing, Lei He
    Fast dual-vdd buffering based on interconnect prediction and sampling. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:95-102 [Conf]
  15. Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu
    Exploiting on-chip data behavior for delay minimization. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:103-110 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002