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Conferences in DBLP

Conference on Very Large Scale Integration (VLSI) (vlsi)
2006 (conf/vlsi/2006soc)

  1. Shekhar Borkar
    Introduction to panel discussion Probabilistic & statistical design - the wave of the future. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:- [Conf]
  2. Jean-Pierre Schoellkopf
    Design challenges for the 45 nm node and below. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:- [Conf]
  3. Jacques Benkowski
    The system is really in the SoC : new investment opportunities. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:- [Conf]
  4. A. Domman
    An overview of where the fields of SoCs, HDI and MEMS are heading to and how to characterize them. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:- [Conf]
  5. Bilge E. S. Akgul, Lakshmi N. Chakrapani, Pinar Korkmaz, Krishna V. Palem
    Probabilistic CMOS Technology: A Survey and Future Directions. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:1-6 [Conf]
  6. Alain J. Martin
    Can Asynchronous Techniques Help the SoC Designer? [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:7-11 [Conf]
  7. Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin
    State-holding in Look-Up Tables: application to asynchronous logic. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:12-17 [Conf]
  8. Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík
    MDCT IP Core Generator with Architectural Model Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:18-23 [Conf]
  9. Marco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini
    A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:24-29 [Conf]
  10. Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro
    Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:30-35 [Conf]
  11. Sam Kavusi, Kunal Ghosh, Abbas El Gamal
    Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:36-41 [Conf]
  12. Shoji Kawahito
    Circuit and Device Technologies for CMOS functional Image Sensors. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:42-47 [Conf]
  13. Robert Henderson, Bruce Rae, David Renshaw, E. Charbon
    Oversampled Time Estimation Techniques for Precision Photonic Detectors. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:48-51 [Conf]
  14. Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi
    Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:52-57 [Conf]
  15. Ramachandruni Venkata Kamala, M. B. Srinivas
    High-Throughput Montgomery Modular Multiplication. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:58-62 [Conf]
  16. Sinan Yalcin, Ilker Hamzaoglu
    A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:63-67 [Conf]
  17. Hsin-Chou Chi, Chia-Ming Wu
    An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:68-73 [Conf]
  18. Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto
    Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:74-79 [Conf]
  19. Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen
    Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:80-85 [Conf]
  20. SangHun Lee, Chanho Lee
    A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:86-91 [Conf]
  21. Hamid Shojaei, Mohammad Sayyaran
    Signal Coverage Computation in Formal Verification. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:92-97 [Conf]
  22. Justin Xu, Cheng-Chew Lim
    Modelling Heterogeneous Interactions in SoC Verification. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:98-103 [Conf]
  23. Shih-Chieh Wu, Chun-Yao Wang
    PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:104-109 [Conf]
  24. Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.
    A Fast SAT Solver Strategy Based on Negated Clauses. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:110-115 [Conf]
  25. Chin-Cheng Kuo, Chien-Nan Jimmy Liu
    On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:116-121 [Conf]
  26. Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira
    Variation-Aware, Library Compatible Delay Modeling Strategy. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:122-127 [Conf]
  27. Renato Fernandes Hentschke, Sandro Sawicki, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis
    An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:128-133 [Conf]
  28. Vagner S. Rosa, Eduardo Costa, Sergio Bampi
    A VHDL Generation Tool for Optimized Parallel FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:134-139 [Conf]
  29. Pablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli
    A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:140-145 [Conf]
  30. Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane
    An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:146-151 [Conf]
  31. Derin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici
    A Predictable Communication Scheme for Embedded Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:152-157 [Conf]
  32. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:158-163 [Conf]
  33. Ulrich Bockelmann
    Detecting DNA by field effect transistor arrays. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:164-168 [Conf]
  34. Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, A. Nascetti, D. Caputo, G. de Cesare
    Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:169-174 [Conf]
  35. Bert Gyselinckx, R. Vullers, C. Van Hoof, J. Ryckaert, R. F. Yazicioglu, P. Fiorini, V. Leonov
    Human++: Emerging Technology for Body Area Networks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:175-180 [Conf]
  36. Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
    Security evaluation of dual rail logic against DPA attacks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:181-186 [Conf]
  37. R. C. Goncalves da Silva, H. I. Boudinov, L. Carro
    A low power high performance CMOS voltage-mode quaternary full adder. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:187-191 [Conf]
  38. Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno
    A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:192-197 [Conf]
  39. Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi
    Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:198-203 [Conf]
  40. Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
    Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:204-209 [Conf]
  41. Senthamaraikannan Raghunath, Syed M. Aziz
    High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:210-215 [Conf]
  42. Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai
    A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:216-221 [Conf]
  43. Sujan Pandey, Nurten Utlu, Manfred Glesner
    Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:222-227 [Conf]
  44. Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi
    Architecture of an HDTV Intraframe Predictor for a H.264 Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:228-233 [Conf]
  45. Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer
    Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:234-238 [Conf]
  46. M. Shah, D. Nagchoudhuri
    BIST Scheme for Low Heat Dissipation and Reduced Test Application Time. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:239-244 [Conf]
  47. Ron Press, Jay Jahangiri
    The Demand and Practical Approach for 100x Test Compression. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:245-250 [Conf]
  48. Ravindra V. Kshirsagar, Rajendra M. Patrikar
    Design of a Reconfigurable Multiprocessor Core for Higher Performance and Reliability of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:251-254 [Conf]
  49. Shampa Chakraverty, Arvind Batra, Aman Rathi
    Directed Convergence Heuristic: A fast & novel approach to Steiner Tree Construction. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:255-260 [Conf]
  50. Beate Muranko, Rolf Drechsler
    Technical Documentation of Software and Hardware in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:261-266 [Conf]
  51. Ramon Tortosa Navas, Antonio Aceituno, José Manuel de la Rosa, Francisco V. Fernández, Ángel Rodríguez-Vázquez
    Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:267-271 [Conf]
  52. Yngvar Berg, Omid Mirmotahari, Snorre Aunet
    Pseudo Floating-Gate Inverter with Feedback Control. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:272-277 [Conf]
  53. Hanene Ben Fradj, Cécile Belleudy, Michel Auguin
    Main Memory Energy Optimization for Multi-Task Applications. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:278-283 [Conf]
  54. Anna Bernasconi, Valentina Ciriani, Roberto Cordone
    EXOR Projected Sum of Products. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:284-289 [Conf]
  55. Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:290-295 [Conf]
  56. Sujan Pandey, Tudor Murgan, Manfred Glesner
    Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:296-301 [Conf]
  57. Tudor Murgan, O. Mitrea, Sujan Pandey, P. B. Bacinschi, Manfred Glesner
    Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:302-307 [Conf]
  58. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
    A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:308-313 [Conf]
  59. Margrit R. Krug, Marcelo S. Lubaszewski, Marcelo de Souza Moraes
    Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:314-319 [Conf]
  60. Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu
    CAT platform for analogue and mixed-signal test evaluation and optimization. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:320-325 [Conf]
  61. Livier Lizzarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur
    Study of a BIST Technique for CMOS Active Pixel Sensors. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:326-331 [Conf]
  62. Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim
    Soft Error Resilient System Design through Error Correction. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:332-337 [Conf]
  63. Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
    Organic Computing at the System on Chip Level. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:338-341 [Conf]
  64. Antonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, B. Kaczer, C. Bruynseraede, Z. Tokei
    Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:342-347 [Conf]
  65. Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo
    A New Phase Noise Model for TSPC based divider. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:348-351 [Conf]
  66. Shan Jiang, Manh Anh Do, Kiat Seng Yeo
    A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:352-356 [Conf]
  67. Yue-Fang Kuo, Ro-Min Weng, Chun-Yu Liu
    A 5.4-GHz Low-Power Swallow-Conterless Frequency Synthesizer with a Nonliear PFD. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:357-360 [Conf]
  68. Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu
    Energy-Effcient Scheduling for Autonomous Mobile Robots. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:361-366 [Conf]
  69. Se Hun Kim, Vincent John Mooney
    Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:367-372 [Conf]
  70. Rodrigo M. Passos, José Augusto Miranda Nacif, Raquel A. F. Mini, Antonio Alfredo Ferreira Loureiro, Antônio Otávio Fernandes, Claudionor N. Coelho
    System-level Dynamic Power Management Techniques for Communication Intensive Devices. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:373-378 [Conf]
  71. Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz
    Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:379-384 [Conf]
  72. K. Schultz, K. Paranjape
    SOC Debug Challenges and Tools. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:385-390 [Conf]
  73. Pierre Vanhauwaert, Régis Leveugle, Philippe Roche
    Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:391-396 [Conf]
  74. Yann Oddos, Katell Morin-Allory, Dominique Borrione
    On-Line Test Vector Generation from Temporal Constraints Written in PSL. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:397-402 [Conf]
  75. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
    Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:403-408 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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