Conferences in DBLP

Conference on Very Large Scale Integration (VLSI) (vlsi)
2005 (conf/vlsi/2005soc)

1. Paul Franzon, David Nackashi, Christian Amsinck, Neil DiSpigna, Sachin Sonkusale
   Molecular Electronics - Devices and Circuits Technology. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:1-10 [Conf]
   
2. G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard
   Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:11-24 [Conf]
   
3. Leonardo L. de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José C. Monteiro, João Baptista Martins, Sergio Bampi, Ricardo Augusto da Luz Reis
   A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:25-39 [Conf]
   
4. Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert
   Defragmentation Algorithms for Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:41-53 [Conf]
   
5. Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin
   Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:55-69 [Conf]
   
6. Chul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian
   3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:71-86 [Conf]
   
7. Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
   Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:87-109 [Conf]
   
8. Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
   A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:111-125 [Conf]
   
9. João M. S. Silva, L. Miguel Silveira
   Issues in Model Reduction of Power Grids. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2005, pp:127-144 [Conf]
   
10. Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen
    A Traffic Injection Methodology with Support for System-Level Synchronization. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:145-161 [Conf]
    
11. Jun-Cheol Park, Vincent John Mooney III
    Pareto Points in SRAM Design Using the Sleepy Stack Approach. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:163-177 [Conf]
    
12. César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis
    Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:179-194 [Conf]
    
13. Jerome Quartana, Laurent Fesquet, Marc Renaudin
    Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:195-207 [Conf]
    
14. Muhsen Aljada, Kamal Alameh, Adam Osseiran, Khalid Al-Begain
    A Novel MicroPhotonic Structure for Optical Header Recognition. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:209-219 [Conf]
    
15. Erik Larsson, Stina Edbom
    Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:221-244 [Conf]
    
16. Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur
    On-chip Pseudorandom Testing for Linear and Nonlinear MEMS. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:245-266 [Conf]
    
17. Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
    Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:267-281 [Conf]
    
18. Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
    On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:283-297 [Conf]
    
19. Rüdiger Ebendt, Rolf Drechsler
    Exact BDD Minimization for Path-Related Objective Functions. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:299-315 [Conf]
    
20. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes
    Current Mask Generation: an Analog Circuit to Thwart DPA Attacks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:317-330 [Conf]
    
21. Cristiano Lazzari, Lorena Anghel, Ricardo Reis
    A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:331-344 [Conf]