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Conferences in DBLP

2006 (conf/arc/2006)

  1. Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner
    Implementation of Realtime and Highspeed Phase Detector on FPGA. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:1-11 [Conf]
  2. Gerd Van den Branden, Geert Braeckman, Abdellah Touhafi, Erik F. Dirkx
    Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:12-17 [Conf]
  3. Rodrigo Piedade, Leonel Sousa
    Configurable Embedded Core for Controlling Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:18-23 [Conf]
  4. J. Gonzalez-Gomez, Ivan Gonzalez, Francisco J. Gomez-Arribas, Eduardo I. Boemo
    Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:24-29 [Conf]
  5. Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
    Dynamic Partial Reconfigurable FIR Filter Design. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:30-35 [Conf]
  6. Rodrigo Agís, Javier Díaz, Eduardo Ros, Richard Carrillo, Eva M. Ortigosa
    Event-Driven Simulation Engine for Spiking Neural Networks on a Chip. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:36-45 [Conf]
  7. Eva M. Ortigosa, Antonio Cañas, R. Rodríguez, Javier Díaz, Sonia Mota
    Towards an Optimal Implementation of MLP in FPGA. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:46-51 [Conf]
  8. Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen De Bosschere, Wilfried Philips
    Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:52-58 [Conf]
  9. Hiren Joshi, S. S. Verma, G. K. Sharma
    Quality Driven Dynamic Low Power Reconfiguration of Handhelds. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:59-64 [Conf]
  10. Joong-ho Park, Bang-Hyun Sung, Seok-Yoon Kim
    An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:65-74 [Conf]
  11. Javier Díaz, Eduardo Ros Vidal, Sonia Mota, Rafael Rodríguez-Gomez
    Highly Paralellized Architecture for Image Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:75-86 [Conf]
  12. Niklas Lepistö, Benny Thörnberg, Mattias O'Nils
    Design Exploration of a Video Pre-processor for an FPGA Based SoC. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:87-92 [Conf]
  13. Sunil Shukla, Neil W. Bergmann, Jürgen Becker
    QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:93-98 [Conf]
  14. Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys, Kevin Skadron
    Applications of Small-Scale Reconfigurability to Graphics Processors. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:99-108 [Conf]
  15. Vanderlei Bonato, José A. de Holanda, Eduardo Marques
    An Embedded Multi-camera System for Simultaneous Localization and Mapping. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:109-114 [Conf]
  16. Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano
    Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:115-121 [Conf]
  17. Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López
    Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:122-127 [Conf]
  18. Slawomir Cichon, Marek Gorgon, Miroslaw Pac
    Handel-C Design Enhancement for FPGA-Based DV Decoder. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:128-133 [Conf]
  19. Alex Ngouanga, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez, Altamiro Amadeu Susin
    Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:134-145 [Conf]
  20. Young-Ho Seo, Dong-Wook Kim
    A New VLSI Architecture of Lifting-Based DWT. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:146-151 [Conf]
  21. Ignacio Bravo, Pedro Jiménez, Manuel Mazo, José Luis Lázaro, Ernesto Martín
    Architecture Based on FPGA's for Real-Time Image Processing. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:152-157 [Conf]
  22. Eduardo Ros Vidal, Javier Díaz, Sonia Mota, F. Vargas-Martín, M. D. Peláez-Coca
    Real Time Image Processing on a Portable Aid Device for Low Vision Patients. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:158-163 [Conf]
  23. Sonia Mota, Eduardo Ros Vidal, Javier Díaz, Francisco de Toro
    General Purpose Real-Time Image Segmentation System. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:164-169 [Conf]
  24. Hui Qin, Tsutomu Sasao, Jon T. Butler
    Implementation of LPM Address Generators on FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:170-181 [Conf]
  25. Rainer Scholz, Klaus Buchenrieder
    Self Reconfiguring EPIC Soft Core Processors. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:182-186 [Conf]
  26. Sara Román, Julio Septién, Hortensia Mecha, Daniel Mozos
    Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:187-192 [Conf]
  27. Mário P. Véstias, Horácio C. Neto
    Area/Performance Improvement of NoC Architectures. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:193-198 [Conf]
  28. Kwangsup So, Jin-Sang Kim, Won-Kyung Cho, Young Soo Kim, Doug Young Suh
    Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:199-204 [Conf]
  29. Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:205-216 [Conf]
  30. Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
    Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:217-229 [Conf]
  31. Domingo Benitez, Juan C. Moure, Dolores I. Rexachs, Emilio Luque
    A Reconfigurable Data Cache for Adaptive Processors. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:230-242 [Conf]
  32. Daniel S. Poznanovic
    The Emergence of Non-von Neumann Processors. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:243-254 [Conf]
  33. Marcelo Götz, Florian Dittmann
    Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:255-261 [Conf]
  34. Manuel G. Gericota, Gustavo R. Alves, Luís F. Lemos, José M. Ferreira
    A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:262-267 [Conf]
  35. Minoru Watanabe, Fuminori Kobayashi
    A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:268-273 [Conf]
  36. Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz
    PISC: Polymorphic Instruction Set Computers. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:274-286 [Conf]
  37. Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara
    Generic Network Interfaces for Plug and Play NoC Based Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:287-298 [Conf]
  38. Nikolay Kavaldjiev, Gerard J. M. Smit, Pascal T. Wolkotte, Pierre G. Jansen
    Providing QoS Guarantees in a NoC by Virtual Channel Reservation. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:299-310 [Conf]
  39. Milan Tichý, Jan Schier, David Gregg
    Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:311-316 [Conf]
  40. Hongzhi Wang, Pierre Leray, Jacques Palicot
    A Reconfigurable Architecture for MIMO Square Root Decoder. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:317-322 [Conf]
  41. Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:323-334 [Conf]
  42. François-Xavier Standaert, François Macé, Eric Peeters, Jean-Jacques Quisquater
    Updates on the Security of FPGAs Against Power Analysis Attacks. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:335-346 [Conf]
  43. Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede
    Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:347-357 [Conf]
  44. Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane
    FPGA Implementation of a GF(2m) Tate Pairing Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:358-369 [Conf]
  45. Guerric Meurice de Dormale, Jean-Jacques Quisquater
    Iterative Modular Division over GF(2m): Novel Algorithm and Implementations on FPGA. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:370-382 [Conf]
  46. David Rodríguez, Juan M. Sánchez, Arturo Duran
    Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:383-388 [Conf]
  47. Sherif Yusuf, Wayne Luk, M. K. N. Szeto, W. Osborne
    UNITE: Uniform Hardware-Based Network Intrusion deTection Engine. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:389-400 [Conf]
  48. Betul Buyukkurt, Zhi Guo, Walid A. Najjar
    Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:401-412 [Conf]
  49. Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar
    Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:413-418 [Conf]
  50. Jie Guo, Gleb Belov, Gerhard Fettweis
    A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:419-424 [Conf]
  51. Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Suk Jin Kim
    Hardware and a Tool Chain for ADRES. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:425-430 [Conf]
  52. Jack Whitham, Neil C. Audsley
    Integrating Custom Instruction Specifications into C Development Processes. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:431-442 [Conf]
  53. Jens Braunes, Rainer G. Spallek
    A Compiler-Oriented Architecture Description for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:443-448 [Conf]
  54. Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro
    Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:449-454 [Conf]
  55. Jae-Jin Lee, Gi-Yong Song
    High-Level Synthesis Using SPARK and Systolic Array. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:455-460 [Conf]
  56. Jae-Jin Lee, Gi-Yong Song
    Super Semi-systolic Array-Based Application-Specific PLD Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:461-466 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002